TP3054-X NSC [National Semiconductor], TP3054-X Datasheet - Page 4

• Manufacturer Part Number: TP3054-X
• Description: Extended Temperature Serial Interface CODEC/Filter COMBO Family
• Manufacturer: NSC [National Semiconductor]

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Functional Description
LONG FRAME SYNC OPERATION
To use the long frame mode, both the frame sync pulses,
FS
with timing relationships specified in Figure 3. Based on the
transmit frame sync, FS
short or long frame sync pulses are being used. For 64 kHz
operation, the frame sync pulse must be kept low for a
minimum of 160 ns. The D
enabled with the rising edge of FS
BCLK
is the sign bit. The following seven BCLK
out the remaining seven bits. The D
the falling BCLK
FS
receive frame sync pulse, FS
D
(BCLK
the long frame sync pulse in synchronous or asynchronous
mode.
In applications where the LSB bit is used for signalling, with
FS
lost LSB as “
TRANSMIT SECTION
The transmit section input is an operational amplifier with
provision for gain adjustment using two external resistors,
see Figure 4. The low noise and wide bandwidth allow gains
in excess of 20 dB across the audio passband to be realized.
The op amp drives a unity-gain filter consisting of RC active
R
X
X
R
to be latched in on the next eight falling edges of BCLK
and FS
going low, whichever comes later. A rising edge on the
two bit clock periods long, the decoder will interpret the
X
X
, whichever comes later, and the first bit clocked out
in synchronous mode). All four devices may utilize
R
1
, must be three or more bit clock periods long,
⁄
2
” to minimize noise and distortion.
X
edge following the eighth rising edge, or by
X
, the COMBO will sense whether
X
R
, will cause the PCM data at
TRI-STATE output buffer is
X
X
or the rising edge of
output is disabled by
X
(Continued)
rising edges clock
R
4
pre-filter, followed by an eighth order switched-capacitor
bandpass filter clocked at 256 kHz. The output of this filter
directly drives the encoder sample-and-hold circuit. The A/D
is of companding type according to µ-law (TP3054) or A-law
(TP3057) coding conventions. A precision voltage reference
is trimmed in manufacturing to provide an input overload
(t
Characteristics). The FS
sampling of the filter output, and then the successive-
approximation encoding cycle begins. The 8-bit code is then
loaded into a buffer and shifted out through D
FS
165 µs (due to the transmit filter) plus 125 µs (due to encod-
ing delay), which totals 290 µs. Any offset voltage due to the
filters or comparator is cancelled by sign bit integration.
RECEIVE SECTION
The receive section consists of an expanding DAC which
drives a fifth order switched-capacitor low pass filter clocked
at 256 kHz. The decoder is A-law (TP3057) or µ-law
(TP3054) and the 5th order low pass filter corrects for the sin
x/x attenuation due to the 8 kHz sample/hold. The filter is
then followed by a 2nd order RC active post-filter/power
amplifier capable of driving a 600Ω load to a level of 7.2
dBm. The receive section is unity-gain. Upon the occurrence
of FS
edge of the next eight BCLK
the decoder time slot, the decoding cycle begins, and 10 µs
later the decoder DAC output is updated. The total decoder
delay is ∼10 µs (decoder update) plus 110 µs (filter delay)
plus 62.5 µs (
MAX
X
pulse. The total encoding delay will be approximately
) of nominally 2.5V peak (see table of Transmission
R
, the data at the D
1
⁄
2
frame), which gives approximately 180 µs.
X
R
input is clocked in on the falling
R
frame sync pulse controls the
(BCLK
X
) periods. At the end of
X
at the next