MC68HC11F1CPU2 FREESCALE [Freescale Semiconductor, Inc], MC68HC11F1CPU2 Datasheet - Page 51

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MC68HC11F1CPU2

Manufacturer Part Number
MC68HC11F1CPU2
Description
MC68HC11F1 Technical Data
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
OPT2 — System Configuration Options 2
GWOM — Port G Wired-OR Mode
CWOM — Port C Wired-OR Mode
CLK4X — 4XOUT Clock Enable
Bits [4:0] — Not implemented
4.3.2.5 Block Protect Register (BPROT)
BPROT — Block Protect
Bits [7:5] — Not implemented
PTCON — Protect for CONFIG
BPRT[3:0] — Block Protect Bits for EEPROM
TECHNICAL DATA
RESET:
RESET:
Refer to SECTION 6 PARALLEL INPUT/OUTPUT.
Refer to SECTION 6 PARALLEL INPUT/OUTPUT.
The 4XOUT signal, when enabled, is a buffered XTAL signal and is four times the fre-
quency of the E-clock. This buffered clock is intended to synchronize external devices
with the MCU. Refer to SECTION 2 PIN DESCRIPTIONS.
Always read zero
BPROT prevents accidental writes to EEPROM and the CONFIG register. The bits in
this register can be written to zero during the first 64 E-clock cycles after reset in the
normal modes. Once the bits are cleared to zero, the EEPROM array and the CONFIG
register can be programmed or erased. Setting the bits in the BPROT register to logic
one protects the EEPROM and CONFIG register until the next reset. Refer to Table
4-6.
Always read zero
0 = Port G operates normally.
1 = Port G outputs are open-drain type.
0 = Port C operates normally.
1 = Port C outputs are open-drain type.
0 = The 4XOUT pin is driven low.
1 = The 4XOUT signal is driven on the 4XOUT pin.
0 = CONFIG register can be programmed or erased normally
1 = CONFIG register cannot be programmed or erased
0 = Protection disabled for associated block
1 = Protection enabled for associated block
GWOM
Bit 7
Bit 7
0
0
CWOM
6
0
6
0
Freescale Semiconductor, Inc.
OPERATING MODES AND ON-CHIP MEMORY
For More Information On This Product,
CLK4X
5
0
5
0
Go to: www.freescale.com
PTCON
4
0
4
1
BPRT3
1
3
0
3
BPRT2
2
0
2
1
BPRT1
1
0
1
1
BPRT0
Bit 0
Bit 0
0
1
$1038
$1035
4-13

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