MC68HC11F1CPU2 FREESCALE [Freescale Semiconductor, Inc], MC68HC11F1CPU2 Datasheet - Page 100

• Manufacturer Part Number: MC68HC11F1CPU2
• Description: MC68HC11F1 Technical Data
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

8.2 SPI Transfer Formats
8-2
During an SPI transfer, data is simultaneously transmitted and received. A serial clock
line synchronizes shifting and sampling of the information on the two serial data lines.
A slave select line allows individual selection of a slave SPI device; slave devices that
are not selected do not interfere with SPI bus activities. On a master SPI device, the
select line can optionally be used to indicate a multiple master bus contention. Refer
to Figure 8-2.
SPSR SPI STATUS REGISTER
2
MCU CLOCK
INTERNAL
DIVIDER
SELECT
4
SPI CONTROL
16
32
SPI INTERRUPT
SPI CLOCK (MASTER)
REQUEST
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 8-1 SPI Block Diagram
SERIAL PERIPHERAL INTERFACE
8
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MSTR
SPE
SPIE
DATA BUS
INTERNAL
MSB
8
8-BIT SHIFT REGISTER
READ DATA BUFFER
SPCR SPI CONTROL REGISTER
8
CLOCK
LOGIC
LSB
CLOCK
S
S
S
M
M
M
CONTROL
LOGIC
PIN
TECHNICAL DATA
MC68HC11F1
MISO/
MOSI/
SCK/
PD2
PD3
PD4
PD5
SS/