MC68HC11F1CPU2 FREESCALE [Freescale Semiconductor, Inc], MC68HC11F1CPU2 Datasheet - Page 121

• Manufacturer Part Number: MC68HC11F1CPU2
• Description: MC68HC11F1 Technical Data
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

PEDGE — Pulse Accumulator Edge Control
Bit 3 — Not implemented
I4/O5 — Input Capture 4/Output Compare
RTR[1:0] — RTI Interrupt Rate Select
9.5 Computer Operating Properly Watchdog Function
9.6 Pulse Accumulator
TECHNICAL DATA
Refer to 9.6 Pulse Accumulator.
Always reads zero
Refer to 9.6 Pulse Accumulator.
These two bits determine the rate at which the RTI system requests interrupts. The
RTI system is driven by an E divided by 2
dependent of the timer prescaler. These two control bits select an additional division
factor. Refer to Table 9-5.
The clocking chain for the COP function, tapped off of the main timer divider chain, is
only superficially related to the main timer system. The CR[1:0] bits in the OPTION
register and the NOCOP bit in the CONFIG register determine the status of the COP
function. One additional register, COPRST, is used to arm and clear the COP watch-
dog reset system. Refer to SECTION 5 RESETS AND INTERRUPTS for a more de-
tailed discussion of the COP function.
The MC68HC11F1 MCUs have an 8-bit counter that can be configured to operate ei-
ther as a simple event counter, or for gated time accumulation, depending on the state
of the PAMOD bit in the PACTL register. Refer to the pulse accumulator block dia-
gram, Figure 9-3.
In the event counting mode, the 8-bit counter is incremented by pulses on an external
pin (PAI). The maximum clocking rate for the external event counting mode is the E
clock divided by two. In gated time accumulation mode, a free-running E-clock
signal drives the 8-bit counter, but only while the external PAI pin is activated. Refer
to Table 9-6. The pulse accumulator counter can be read or written at any time.
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TIMING SYSTEM
13
rate clock that is compensated so it is in-
9-15
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