KM681000 SAMSUNG [Samsung semiconductor], KM681000 Datasheet - Page 9

• Manufacturer Part Number: KM681000
• Description: 128K x8 bit Low Power CMOS Static RAM
• Manufacturer: SAMSUNG [Samsung semiconductor]

KM681000B Family
TIMING WAVEFORM OF WRITE CYCLE (2)
FUNCTIONAL DESCRIPTION
* X means don't care
CS
H
X
L
L
L
Address
CS1
CS2
WE
Data in
Data out
NOTES
1. A write occurs during the overlap of low CS
2.
3.
4.
1
going low. A write ends at the earliest transition among CS
t
t
t
ends at CS
to the end of write.
CW is measured from the later of CS
AS is measured from the address calid to the beginning of write.
WR is measured from the end of write to the address change.
(WRITE CYCLE)
2
going to low.
CS
X
H
H
H
L
2
WE
H
H
X
X
L
1
going low or CS
High-Z
1
, high CS
OE
t
X
X
H
X
L
AS(3)
(CS
2
and low WE. A write begins at the latest transition among CS
2
going high to the end of write.
2
Controlled)
1
going high, CS
t
WR1 applied in case a write ends at CS
Output Disable
Power Down
Power Down
Mode
Read
Write
t
2
AW
going low and WE going high,
t
WC
t
CW(2)
t
CW(2)
t
WP(1)
t
Data Valid
DW
1
, or WE going high,
I/O Pin
High-Z
High-Z
High-Z
Dout
Din
t
WP is measured from the beginning or write
t
DH
1
going low, CS
High-Z
t
WR2(4)
t
WR2 applied in case a write
PRELIMINARY
CMOS SRAM
2
going high and WE
Current Mode
I
I
SB
SB
I
I
I
CC
CC
CC
,I
,I
SB1
SB1
Revision 0.3
April 1996