DP83848YB_08 NSC [National Semiconductor], DP83848YB_08 Datasheet - Page 72
DP83848YB_08
Manufacturer Part Number
DP83848YB_08
Description
Manufacturer
NSC [National Semiconductor]
Datasheet
1.DP83848YB_08.pdf
(84 pages)
- Current page: 72 of 84
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8.2.13 10 Mb/s Serial Mode Transmit Timing
8.2.14 10 Mb/s Serial Mode Receive Timing
Note: RX_CLK may be held high for a longer period of time during transition between reference and recovered clocks.
Minimum high and low times will not be violated.
T2.13.1
T2.13.2
T2.13.3
T2.13.4
T2.14.1
T2.14.2
Parameter
Parameter
RX_CLK
RXD[0]
RX_DV
TX_CLK High Time
TX_CLK Low Time
TXD_0, TX_EN Data Setup to TX_CLK rise
TXD_0, TX_EN Data Hold from TX_CLK rise
RX_CLK High/Low Time
RX_CLK fall to RXD_0, RX_DV Delay
TX_CLK
TX_EN
TXD[0]
Description
Description
T2.13.1
T2.13.3
T2.14.2
T2.14.1
Valid Data
72
Valid Data
10 Mb/s Serial mode
10 Mb/s Serial mode
10 Mb/s Serial mode
10 Mb/s Serial mode
10 Mb/s Serial mode
T2.13.4
Notes
Notes
T2.14.1
T2.13.2
Min
-10
35
Min
20
70
25
0
Typ
50
Typ
25
75
Max
65
10
Max Units
30
80
Units
ns
ns
ns
ns
ns
ns
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