CY8C38_1105 CYPRESS [Cypress Semiconductor], CY8C38_1105 Datasheet - Page 117
CY8C38_1105
Manufacturer Part Number
CY8C38_1105
Description
Programmable System-on-Chip (PSoC) Multiply and divide instructions
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
1.CY8C38_1105.pdf
(130 pages)
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11.9.4 External Crystal Oscillator
Table 11-84. ECO AC Specifications
11.9.5 External Clock Reference
Table 11-85. External Clock Reference AC Specifications
11.9.6 Phase-Locked Loop
Table 11-86. PLL DC Specifications
Table 11-87. PLL AC Specifications
Document Number: 001-11729 Rev. *S
F
I
Fpllin
Fpllout
Jperiod-rms Jitter (rms)
Notes
Parameter
Parameter
Parameter
DD
Parameter
56. This specification is guaranteed by testing the PLL across the specified range using the IMO as the source for the PLL.
57. PLL input divider, Q, must be set so that the input frequency is divided down to the intermediate frequency range. Value for Q ranges from 1 to 16.
58. Based on device characterization (Not production tested).
Crystal frequency range
External frequency range
Input duty cycle range
Input edge rate
PLL operating current
PLL input frequency
PLL intermediate frequency
PLL output frequency
Lock time at startup
[58]
Description
Description
Description
Description
[56]
[56]
[57]
Measured at V
V
In = 3 MHz, Out = 67 MHz
In = 3 MHz, Out = 24 MHz
Output of prescaler
IL
to V
[58]
IH
Conditions
Conditions
Conditions
Conditions
DDIO
/2
PSoC
Min
0.1
Min
30
0
Min
Min
4
24
–
–
1
1
–
–
®
3: CY8C38 Family
Typ
Typ
50
–
–
Typ
400
200
Typ
–
–
–
–
–
–
Data Sheet
Max
Max
33
70
25
–
Max
Max
250
250
48
67
Page 117 of 130
–
–
3
Units
Units
MHz
V/ns
MHz
Units
Units
MHz
MHz
MHz
%
µA
µA
µs
ps
[+] Feedback
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