PIC17C756A MICROCHIP [Microchip Technology], PIC17C756A Datasheet - Page 228

• Manufacturer Part Number: PIC17C756A
• Description: High-Performance 8-bit CMOS EPROM Microcontrollers with 10-bit A/D
• Manufacturer: MICROCHIP [Microchip Technology]

PIC17C7XX
TABLRD
Example1:
Example2:
DS30289B-page 228
Before Instruction
After Instruction (table write completion)
Before Instruction
After Instruction (table write completion)
REG
TBLATH
TBLATL
TBLPTR
MEMORY(TBLPTR)
REG
TBLATH
TBLATL
TBLPTR
MEMORY(TBLPTR)
REG
TBLATH
TBLATL
TBLPTR
MEMORY(TBLPTR)
REG
TBLATH
TBLATL
TBLPTR
MEMORY(TBLPTR)
Table Read
TABLRD
TABLRD
1, 1, REG ;
0, 0, REG ;
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
0x53
0xAA
0x55
0xA356
0x1234
0xAA
0x12
0x34
0xA357
0x5678
0x53
0xAA
0x55
0xA356
0x1234
0x55
0x12
0x34
0xA356
0x1234
TABLWT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Note:
operation
Decode
Q1
No
The MCLR/V
voltage for successful programming of internal
memory.
If MCLR/V
the programming sequence of internal memory
will be interrupted. A short write will occur (2
T
affected.
CY
). The internal memory location will not be
(Table Pointer
on Address
register 'f'
operation
Table Write
[ label ] TABLWT t,i,f
0
i
t
If t = 0,
f
If t = 1,
f
TBLAT
If i = 1,
TBLPTR + 1
If i = 0,
TBLPTR is unchanged
None
1.
2.
3.
1
2 (many if write is to on-chip
EPROM program memory)
Read
bus)
PP
Q2
No
1010
[0,1]
[0,1]
PP
f
= V
TBLATL;
TBLATH;
Load value in ’f’ into 16-bit table
latch (TBLAT)
If t = 1: load into high byte;
If t = 0: load into low byte
The contents of TBLAT are writ-
ten to the program memory
location pointed to by TBLPTR.
If TBLPTR points to external
program memory location, then
the instruction takes two-cycle.
If TBLPTR points to an internal
EPROM
instruction is terminated when
an interrupt is received.
The TBLPTR can be automati-
cally incremented
If i = 1; TBLPTR is not
If i = 0; TBLPTR is incremented
pin must be at the programming
2000 Microchip Technology Inc.
255
DD
Prog Mem (TBLPTR);
11ti
operation
Process
incremented
Data
Q3
No
location,
TBLPTR
ffff
(Table Latch on
WR goes low)
Address bus,
TBLATH or
operation
then
TBLATL
register
Write
Q4
No
ffff
the