MC68HC05L28B MOTOROLA [Motorola, Inc], MC68HC05L28B Datasheet - Page 88

• Manufacturer Part Number: MC68HC05L28B
• Description: Flexible general-purpose microcomputer
• Manufacturer: MOTOROLA [Motorola, Inc]

8
MSTA — Master/slave mode select
This bit is cleared on reset. When MSTA is changed from 0 to a 1, a START signal is generated on the
bus and the master mode is selected. When this bit changes from a 1 to a 0, a STOP signal is
generated and the slave mode is selected. In master mode, clearing MSTA and then immediately
setting it generates a repeated START signal without generating a STOP signal (see Figure 8-1).
MTX — Transmit/receive mode select
TXAK — Transmit acknowledge bit
This bit only has meaning in master receive mode.
Bits 2–0 — not implemented; always read zero.
8.4.4
Bits in this register can be read at any time; Bits 4 and 1 can be cleared at any time.
MCF — Data transferring
MAAS — I
This bit is set when the address of the I
interrupt is generated providing the MIEN bit in the MCR register is set; the CPU then selects its
transmit/receive mode according to the state of the SRW bit. Writing to the MCR register clears this bit.
MOTOROLA
8-8
I
2
C-bus status register (MSR)
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
2
C-bus addressed as a slave
I
2
C-bus status register (MSR)
–
–
–
–
–
Master mode; send START signal when set.
Slave mode; send STOP signal when cleared.
Transmit mode.
Receive mode.
No acknowledge signal response.
An acknowledge signal will be sent to the bus at the ninth clock bit
after receiving one byte of data.
Data transmit complete.
Data is being transferred.
I
I
2
2
C-bus is addressed as a slave.
C-bus is not addressed.
Address bit 7
$0013
MCF MAAS MBB
2
C-bus (specified in MADR) matches the calling address. An
I
bit 6
2
C-BUS
bit 5
MAL
bit 4
bit 3
SRW
bit 2
MIF
bit 1
MC68HC05L28
RXAK 1000 u001
bit 0
on reset
State
TPG