MC68HC05L28B MOTOROLA [Motorola, Inc], MC68HC05L28B Datasheet - Page 55
MC68HC05L28B
Manufacturer Part Number
MC68HC05L28B
Description
Flexible general-purpose microcomputer
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC05L28B.pdf
(156 pages)
- Current page: 55 of 156
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5.3.2
The core timer counter register is a read-only register, which contains the current value of the 8-bit
ripple counter at the beginning of the timer chain.
Reset clears this register.
5.4
The CPU clock halts during the WAIT mode, but the core timer remains active. If the interrupts are
enabled, then a CTIMER interrupt will cause the processor to exit the WAIT mode.
5.5
The timer is cleared when going into STOP mode. When STOP is exited by an external interrupt
or an external reset, the internal oscillator will restart, followed by an internal processor
stabilization delay (t
MC68HC05L28
Core timer counter (CTCR)
Core timer counter register (CTCR)
Core timer during WAIT
Core timer during STOP
PORL
). The timer is then cleared and operation resumes.
Address
$0009
bit 7
CORE TIMER
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
MOTOROLA
0000 0000
on reset
State
TPG
5-5
5
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