MPC8347 FREESCALE [Freescale Semiconductor, Inc], MPC8347 Datasheet - Page 50

• Manufacturer Part Number: MPC8347
• Description: Integrated Host Processor Hardware Specifications
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

I
Figure 30
Figure 31
50
2
C
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Bus free time between a STOP and START condition
Noise margin at the LOW level for each connected device (including hysteresis)
Noise margin at the HIGH level for each connected device (including hysteresis)
Notes:
1. The symbols for timing specifications follow the pattern of t
2. MPC8347EA provides a hold time of at least 300 ns for the SDA signal (referred to the V
3. The maximum t
4. C
and t
respect to the time data input signals (D) reach the valid state (V) relative to the t
(H) state or setup time. Also, t
(S) goes invalid (X) relative to the t
I
clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the
appropriate letter: R (rise) or F (fall).
the undefined region of the falling edge of SCL.
2
SDA
C timing (I2) for the time that the data with respect to the stop condition (P) reaches the valid state (V) relative to the t
SCL
B
MPC8347EAMPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3
= capacitance of one bus line in pF.
(first two letters of functional block)(reference)(state)(signal)(state)
provides the AC test load for the I
shows the AC timing diagram for the I
S
t
I2DVKH
I2CF
t
I2CL
t
I2SXKL
must be met only if the device does not stretch the LOW period (t
Output
Table 42. I
I2SXKL
Parameter
I2C
symbolizes I
Figure 31. I
clock reference (K) going to the low (L) state or hold time. Also, t
t
I2DXKL
2
C AC Electrical Specifications (continued)
Figure 30. I
Z
t
I2DVKH
0
= 50 Ω
t
2
2
I2CH
C timing (I2) for the time that the data with respect to the start condition
2
C.
C Bus AC Timing Diagram
t
2
I2SXKL
2
C bus.
C AC Test Load
for outputs. For example, t
(first two letters of functional block)(signal)(state) (reference)(state)
Sr
t
I2SVKH
t
I2KHKL
R
L
= 50 Ω
Symbol
t
t
I2PVKH
I2KHDX
I2C
t
t
V
V
I2CR
I2CF
NH
NL
I2DVKH
clock reference (K) going to the high
t
I2PVKH
OV
1
IHmin
I2CL
symbolizes I
DD
t
20 + 0.1 C
20 + 0.1 C
I2CR
0.1 × OV
0.2 × OV
) of the SCL signal.
/2
of the SCL signal) to bridge
Min
0.6
1.3
Freescale Semiconductor
P
DD
DD
b
b
I2PVKH
2
t
4
4
I2CF
C timing (I2) with
Max
300
300
—
—
—
—
symbolizes
S
for inputs
Unit
ns
ns
μs
μs
V
V
I2C