MPC8347 FREESCALE [Freescale Semiconductor, Inc], MPC8347 Datasheet - Page 5

no-image

MPC8347

Manufacturer Part Number
MPC8347
Description
Integrated Host Processor Hardware Specifications
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8347CVRADDB
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC8347CVRAGD
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC8347CVRAGD
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
MPC8347CVRAGDB
Manufacturer:
FREESCA
Quantity:
13
Part Number:
MPC8347CVRAGDB
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC8347CVRAGDB
Manufacturer:
FREESCALE
Quantity:
8 000
Part Number:
MPC8347CVVAGDB
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC8347CVVAJDB
Manufacturer:
FREESCAL
Quantity:
194
Part Number:
MPC8347CZQAGD
Manufacturer:
MOTOROLA
Quantity:
490
Part Number:
MPC8347CZQAGDB
Manufacturer:
FREESCAL
Quantity:
354
Part Number:
MPC8347CZQAGDB
Manufacturer:
FREESCALE
Quantity:
20 000
Company:
Part Number:
MPC8347CZQAGDB
Quantity:
180
Freescale Semiconductor
— High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations
— Direct connection to a high-speed device without an external hub
— External PHY with serial and low-pin count (ULPI) interfaces
Local bus controller (LBC)
— Multiplexed 32-bit address and data operating at up to 133 MHz
— Eight chip selects for eight external slaves
— Up to eight-beat burst transfers
— 32-, 16-, and 8-bit port sizes controlled by an on-chip memory controller
— Three protocol engines on a per chip select basis:
— Parity support
— Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)
Programmable interrupt controller (PIC)
— Functional and programming compatibility with the MPC8260 interrupt controller
— Support for 8 external and 35 internal discrete interrupt sources
— Support for 1 external (optional) and 7 internal machine checkstop interrupt sources
— Programmable highest priority request
— Four groups of interrupts with programmable priority
— External and internal interrupts directed to host processor
— Redirects interrupts to external INTA pin in core disable mode.
— Unique vector number for each interrupt source
Dual industry-standard I
— Two-wire interface
— Multiple master support
— Master or slave I
— On-chip digital filtering rejects spikes on the bus
— System initialization data optionally loaded from I
DMA controller
— Four independent virtual channels
— Concurrent execution across multiple channels with programmable bandwidth control
— Handshaking (external control) signals for all channels: DMA_DREQ[0:3],
— All channels accessible to local core and remote PCI masters
– Enhanced host controller interface (EHCI) compatible
– Complies with USB specification Rev. 2.0
– General-purpose chip select machine (GPCM)
– Three user-programmable machines (UPMs)
– Dedicated single data rate SDRAM controller
hardware
DMA_DACK[0:3], DMA_DDONE[0:3]
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3
2
C mode support
2
C interfaces
2
C-1 EPROM by boot sequencer embedded
Overview
5

Related parts for MPC8347