CY8C20X96 CYPRESS [Cypress Semiconductor], CY8C20X96 Datasheet - Page 2

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CY8C20X96

Manufacturer Part Number
CY8C20X96
Description
CapSense Applications
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
Logic Block Diagram
Document Number: 001-12696 Rev. *F
USB
Controller
Interrupt
SRAM
SYSTEM BUS
1K/2K
6/12/24 MHz Internal Main Oscillator
PSoC CORE
SYSTEM BUS
Slave
I2C
CAPSENSE
SYSTEM
Comparators
References
Two
Supervisory ROM (SROM)
Internal
Voltage
(IMO)
Port 4
SYSTEM RESOURCES
Multiple Clock Sources
System
Resets
Port 3
CPU Core (M8C)
CapSense
Module
Port 2
POR
LVD
and
Nonvolatile Memory
8K/16K/32K Flash
Internal Low Speed Oscillator (ILO)
Global Analog Interconnect
Port 1
Master/
Slave
SPI
Port 0
Analog
Reference
Mux
Analog
Programmable
Three 16-Bit
1.8/2.5/3V
Timers
LDO
Sleep and
Watchdog
CY8C20X36/46/66/96
(Regulator)
PWRSYS
Clocks
Digital
Page 2 of 39
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