CY8C20X37 CYPRESS [Cypress Semiconductor], CY8C20X37 Datasheet - Page 9

• Manufacturer Part Number: CY8C20X37
• Manufacturer: CYPRESS [Cypress Semiconductor]

24-pin QFN (20 Sensing Inputs)
Table 3. Pin Definitions – CY8C20337, CY8C20347/S
Document Number: 001-69257 Rev. *F
Notes
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CP
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Pin
No.
9. The center pad (CP) on the QFN package must be connected to ground (V
10. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
11. Alternate SPI clock.
it must be electrically floated and not connected to any other signal.
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I
alternate pins if you encounter issues.
Digital Analog
IOHR
IOHR
IOHR
IOHR
IOHR
IOHR
IOHR
IOHR
IOH
IOH
IOH
IOH
IOH
IOH
I/O
I/O
I/O
I/O
I/O
Power
Power
Power
Power
Type
Input
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Name
P2[5]
P2[3]
P2[1]
P1[7]
P1[5]
P1[3]
P1[1]
NC
V
P1[0]
P1[2]
P1[4]
P1[6]
XRES Active high external reset
P2[2]
P2[4]
P0[0]
P0[2]
P0[4]
V
P0[7]
P0[3]
V
P0[1]
V
SS
DD
SS
SS
Crystal output (XOut)
Crystal input (XIn)
I
I
SPI CLK
ISSP CLK
MOSI
No connection
Ground connection
ISSP DATA
CLK
Driven Shield Output
(optional)
Optional external clock input
(EXTCLK)
with internal pull-down
Driven Shield Output
(optional)
Driven Shield Output
(optional)
Driven Shield Output
(optional)
Supply voltage
Integrating input
Ground connection
Integrating input
Center pad must be
connected to ground
2
2
C SCL, SPI SS
C SDA, SPI MISO
[11]
Description
[10]
[10]
, I
, I
2
2
C SCL, SPI
C SDA, SPI
[9]
SS
) for best mechanical, thermal, and electrical performance. If not connected to ground,
AI, I2C SDA, SPI MISO, P1[5]
Figure 4. CY8C20337, CY8C20347/S Device
AI, I2C SCL, SPI SS, P1[7]
CY8C20x37/37S/47/47S/67/67S
AI, SPI CLK, P1[3]
AI, XOut, P2[5]
AI, XIn, P2[3]
AI, P2[1]
1
4
2
3
5
6
(Top View)
QFN
13
18
17
16
15
14
P0[2], AI
P0[0], AI
P2[4], AI
P2[2], AI
P1[6], AI
XRES
Page 9 of 39
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C bus. Use