CY8C20X37 CYPRESS [Cypress Semiconductor], CY8C20X37 Datasheet - Page 8

• Manufacturer Part Number: CY8C20X37
• Manufacturer: CYPRESS [Cypress Semiconductor]

16-pin QFN (12 Sensing Inputs)
Table 2. Pin Definitions – CY8C20237, CY8C20247/S
Document Number: 001-69257 Rev. *F
Notes
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Pin
No.
6. No center pad.
7. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
8. Alternate SPI clock.
10
12
13
14
15
16
11
1
2
3
4
5
6
7
8
9
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I
alternate pins if you encounter issues.
Digital
IOHR
IOHR
IOHR
IOHR
IOHR
IOHR
IOHR
IOH
IOH
IOH
IOH
I/O
I/O
Power
Power
Type
Input
Analog
I
I
I
I
I
I
I
I
I
I
I
I
I
Name
XRES Active high external reset with
P2[5] Crystal output (XOut)
P2[3] Crystal input (XIn)
P1[7] I
P1[5] I
P1[3] SPI CLK
P1[1] ISSP CLK
P1[0] ISSP DATA
P1[2] Driven Shield Output (optional)
P1[4] Optional external clock
P0[4]
P0[7]
P0[3] Integrating input
P0[1] Integrating input
V
V
DD
SS
MOSI
Ground connection
CLK
(EXTCLK)
internal pull-down
Supply voltage
2
2
C SCL, SPI SS
C SDA, SPI MISO
[8]
Description
[7]
[7]
, I
, I
2
C SCL, SPI
2
C SDA, SPI
[6]
AI , I2 C SDA, SPI MISO, P1[5]
Figure 3. CY8C20237, CY8C20247/S Device
AI , I2 C SCL, SPI SS, P1[7]
CY8C20x37/37S/47/47S/67/67S
AI , XOut, P2[5]
AI , XIn, P2[3]
1
2
3
4
(Top View)
QFN
12
10
11
9
P0[4] , AI
P1[2] , AI
XRES
P1[4] , EXTCLK, AI
Page 8 of 39
2
C bus. Use