CY8C20X36A CYPRESS [Cypress Semiconductor], CY8C20X36A Datasheet - Page 9

• Manufacturer Part Number: CY8C20X36A
• Description: CapSense Applications Operating Range: 1.71 V to 5.5 V
• Manufacturer: CYPRESS [Cypress Semiconductor]

24-Pin QFN with USB
Table 3. Pin Definitions – CY8C20396A PSoC Device
Document Number: 001-54459 Rev. *E
Notes
LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output
Pin No.
8. The center pad (CP) on the QFN package must be connected to ground (V
9. On power-up , the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1])line drives
10. Alternate SPI clock.
CP
10
12
13
14
15
16
17
18
19
20
21
22
23
24
11
1
2
3
4
5
6
7
8
9
it must be electrically floated and not connected to any other signal.
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
Digital
RESET INPUT
IOHR
IOHR
IOHR
IOHR
IOHR
IOHR
IOHR
IOHR
IOH
IOH
IOH
IOH
IOH
IOH
IOH
IOH
I/O
I/O
I/O
I/O
I/O
Power
Power
Power
Type
Analog
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Name
XRES
P2[5]
P2[3]
P2[1]
P1[7]
P1[5]
P1[3]
P1[1]
P1[0]
P1[2]
P1[4]
P1[6]
P0[0]
P0[2]
P0[4]
P0[6]
P0[7]
P0[5]
P0[3]
P0[1]
V
V
V
D+
D-
SS
DD
SS
I
I
SPI CLK
ISSP CLK
MOSI
Ground
USB D+
USB D-
Supply
ISSP DATA
CLK
Optional external clock input
(EXTCLK)
Active high external reset with
internal pull-down
Integrating input
Integrating input
Thermal pad must be
connected to Ground
2
2
C SCL, SPI SS
C SDA, SPI MISO
[10]
Description
[9]
[9]
, I
, I
2
C SCL, SPI
2
C SDA, SPI
[
8
]
SS
) for best mechanical, thermal, and electrical performance. If not connected to ground,
AI, I2C SDA , SPI MISO , P1[5]
AI, I 2 C SCL, SPI SS, P1[7]
Figure 4. CY8C20396A PSoC Device
AI, SPI CLK , P1[3]
P2 [ 5 ], AI
CY8C20X36A/46A/66A/96A
P2 [ 3], AI
P2 [ 1], AI
1
4
2
3
5
6
(Top View)
QFN
18
17
16
14
15
13
P0[2], AI
XRES
P1[6], AI
P1[2 ], AI
P0[0], AI
P1[4] , AI, EXTCLK
Page 9 of 43
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