CY8C20X36A CYPRESS [Cypress Semiconductor], CY8C20X36A Datasheet - Page 15

• Manufacturer Part Number: CY8C20X36A
• Description: CapSense Applications Operating Range: 1.71 V to 5.5 V
• Manufacturer: CYPRESS [Cypress Semiconductor]

48-Pin QFN with USB
Table 9. Pin Definitions – CY8C20646A, CY8C20666A PSoC Device
Document Number: 001-54459 Rev. *E
Notes
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.
24. On Power-up , the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1])line drives
25. The center pad (CP) on the QFN package must be connected to ground (V
26. Alternate SPI clock.
resistive low for 512 sleep clock cycles and both the pins transition to High impedance state . On reset, after XRES de- asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. In both cases, a pull-up resistance on these lines combines with the pull-down resistance
(5.6K ohm) and form a potential divider. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues.
it must be electrically floated and not connected to any other signal.
IOHR
IOHR
IOHR
IOHR
IOHR
IOHR
IOHR
IOHR
IOH
IOH
IOH
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Power
Power
Input
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
NC
P2[7]
P2[5]
P2[3]
P2[1]
P4[3]
P4[1]
P3[7]
P3[5]
P3[3]
P3[1]
P1[7]
P1[5]
NC
NC
P1[3]
P1[1]
V
D+
D-
V
P1[0]
P1[2]
P1[4]
P1[6]
XRES
P3[0]
P3[2]
P3[4]
P3[6]
P4[0]
P4[2]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
SS
DD
No connection
Crystal output (XOut)
Crystal input (XIn)
I
I
No connection
No connection
SPI CLK
ISSP CLK
Ground connection
USB D+
USB D-
Supply voltage
ISSP DATA
Optional external clock input (EXTCLK)
pull-down
Active high external reset with internal
2
2
C SCL, SPI SS
C SDA, SPI MISO
[
24
[
24
]
, I
]
, I
2
C SCL, SPI MOSI
2
C SDA, SPI CLK
[
26
]
40
41
42
43
44
45
46
47
48
CP
SS
) for best mechanical, thermal, and electrical performance. If not connected to ground,
IOH
IOH
IOH
IOH
IOH
AI, I2 C SCL, SPI SS, P1[7]
Figure 10. CY8C20646A, CY8C20666A PSoC Device
Power
Power
Power
I
I
I
I
I
[24, 25]
AI, XOut, P2[5]
AI, XIn , P2[3]
P0[6]
V
NC
NC
P0[7]
P0[5]
P0[3]
V
P0[1]
V
DD
SS
SS
AI , P2[7]
AI , P2[1]
AI , P4[3]
AI , P4[1]
AI , P3[7]
AI , P3[5]
AI , P3[3]
AI , P3[1]
NC
Supply voltage
No connection
No connection
Integrating input
Ground connection
Center pad must be connected to ground
CY8C20X36A/46A/66A/96A
1
2
3
4
5
6
7
8
9
10
11
12
( Top View )
QFN
36
35
34
33
32
31
30
29
28
27
26
25
Page 15 of 43
P2[6] , AI
P2[4] , AI
P2[2] , AI
P2[0] , AI
P4[2] , AI
P4[0] , AI
P3[6] , AI
P3[4] , AI
P3[2] , AI
P3[0 ] , AI
P1[6] , AI
XRES
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