XE88LC01MI000 ETC1 [List of Unclassifed Manufacturers], XE88LC01MI000 Datasheet

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... MTP, 520 Byte RAM • RC and crystal oscillators • 5 reset, 18 interrupt, 8 event sources • 100 years MTP Flash retention at 55°C Ordering Information Reference Memory type Temperature XE88LC01MI000 MTP Flash XE88LC01MI027 MTP Flash XE88LC01MI032 MTP Flash XE88LC01RI000 ROM XE88LC01RI027 ROM ...

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Cool Solutions for Wireless Connectivity XEMICS SA, email: info@xemics.com web: www.xemics.com ...

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Detailed Pin Description 42 1 packaging date production 7 lot identification Figure 1.1: Pinout of the XE88LC01 in LQFP44 package Position Function in name TQFP44 1 PA(5) 2 PA(6) ...

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Position Function in name TQFP44 27 AC_A(3) 28 AC_A(2) 29 AC_A(1) 30 AC_A(0) 31 AC_R(1) 32 AC_R( Vreg 36 RESET 37 Vmult 38 OscIn 39 OscOut 40 PA(0) 41 PA(1) 42 PA(2) 43 PA(3) 44 PA(4) Table ...

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Absolute maximum ratings Stresses beyond these listed in this chapter may cause permanent damage to the device. No functional operation is implied at or beyond these conditions. Exposure to these conditions for an extended period may affect the device ...

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Electrical Characteristics All specification are -40°C to 85°C unless otherwise noted. ROM operates up to 125°C. Operation conditions Power supply Operating speed Instruction cycle Current requirement Current requirement MTP Flash memory Table 3.1: Specifications and current requirement of the ...

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CPU The XE88LC01 CPU is a low power RISC core. It has 16 internal registers for efficient imple- mentation of the C compiler. Its instruction set is made of 35 generic instructions, all coded on 22 bits, with 8 ...

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Memory organisation The CPU uses a Harvard architecture, so that memory is organised in two separated fields: program memory and data memory. As both memory are separated, the central processing unit can read/write data at the same time it ...

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Data memory The data memory is implemented as static Random-Access Memory (RAM). The RAM size is 512 x 8 bits plus 8 low power RAM bytes that require very low current when addressed. Pro- grams using the low-power RAM ...

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Resets The reset source name is simplified in the following registers description. Name mapping is in the next table. reset source resetsystem resetSynch resetPOR resetCold resetPad resetPconf resetSleep Table 6.2: Reset signal name mapping 6.3 Low power RAM Low ...

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System, oscillators, prescaler and watchdog Name 7 6 Address RegSysCtrl SleepEn EnRes-PConf EnBus-Error h0010, type 1 rw, 0 por rw, 0 cold RegSysReset Sleep ResPor h0011, type cold r, 0 RegSysClock CpuSel ExtClk h0012, type 1 ...

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PortB Name 7 6 Address RegPBOut PBOut(7) PBOut(6) h0028 rw, 0 pconf rw, 0 pconf RegPBIn PBIn(7) PBIn(6) h0029 r r RegPBDir PBDir(7) PBDir(6) h002A rw, 0 pconf rw, 0 pconf RegPBOpen PBOpen(7) PBOpen(6) h002B rw, 0 pconf rw, ...

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Events Name 7 Address RegEvn EvnCntA EvnCntC h003C rc1, 0 global rc1, 0 global RegEvnEn EvnEnCntA EvnEnCntC h003D rw, 0 global rw, 0 global RegEvnPriority EvnPriority(7) EvnPriority(6) EvnPriority(5) EvnPriority(4) EvnPriority(3) EvnPriority(2) EvnPriority(1) EvnPriority(0) h003E r,1 global r,1 global RegEvnEvn ...

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UART Name 7 Address RegUartCtrl UartEcho UartEnRx h0050 rw, 0 global rw, 0 global RegUartCmd SelXtal UartWakeup h0051 rw, 0 global rw, 0 global RegUartTx UartTx(7) UartTx(6) h0052 rw, 0 global rw, 0 global RegUartTxSta h0053 RegUartRx UartRx(7) UartRx(6) ...

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Acquisition chain Name 7 Address RegAcOutLsb AdcOutL(7) AdcOutL(6) h0060 r RegAcOutMsb AdcOutM(7) AdcOutM(6) h0061 r RegAcCfg0 Start NelConv(1) h0062 r0w, 0 global rw, 0 global RegAcCfg1 IbAmpADC(1) IbAmpAdc(0) h0063 rw, 1 global rw, 1 global RegAcCfg2 Fin(1) Fin(0) h0064 ...

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Peripherals The XE88LC01 includes usual microcontroller peripherals and some other blocks more spe- cific to low-voltage or mixed-signal operation. They are 3 parallel ports, one input port (A), one IO and analog port (B) with analog switching capabilities and ...

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Xtal clock The Xtal Oscillator operates with an external crystal of 32’768 Hz. symbol description f_clk32k nominal frequency st_x32k oscillator start-up time duty_clk32k duty cycle on the digital output relative frequency deviation from nominal, for a crystal with CL=8.2 ...

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F frequency at start-up st range range selection mult[3:0] coarse tuning range fine tuning range tune[5:0] fine tuning step T start-up time st O overshoot at start- wakeup time wu O overshoot at wakeup wu jit ...

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Voltage level detector • Can be switched off simultaneously with CPU activities • Generates an interrupt if power supply is below a pre-determined level The Voltage Level Detector monitors the state of the system battery. It returns ...

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ZoomingADC The fully differential acquisition chain is formed of a programmable gain (0.5 - 1000) and offset amplifier and a programmable speed and resolution ADC (example: 12 bits at 4 kHz, 16 bits at 1 kHz). It can handle ...

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PGA2 sym description GD2 PGA2 Signal Gain GDoff2 PGA2 Offset Gain GDoff2_step GDoff2(code+1) – GDoff2(code) GD_preci Precision on gain settings GD_TC Temperature dependency of gain settings fs Input sampling frequency Zin2 Input impedance VN2 Input referred noise Table 8.2: ...

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Analog to digital converter (ADC) The whole analog to digital conversion sequence is basically made of an initialisation, a set of Nelconv elementary incremental conversions and finally a termination phase bits on RegACCfg0). The result is a ...

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NResol is the maximal readable resolution of the digital filter. 8.6 resolution conditions oversampling per convertion = conversion (no offset rejection) oversampling per convertion = ...

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ADC converter (GDtot = 1) (version v5a) Vbat = Vref = 5.0V 500kHz; OSR = 32; NELCONV = 2MHz; IB_AMP(1:0) = 11; Vinn= sweep = 1201; average on 4 samples ...

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ADC converter (GDtot = 20) (version v5a) Vbat = Vref = 5.0V 500kHz; OSR = 32; NELCONV = 2MHz; IB_AMP(1:0) = 11; Vinn= sweep = 1201; average on 4 samples ...

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Integral Non-Linearity (INL) and Differential Non-Linearity (DNL) for 16-bit reso- lution 16 bits - ADC converter (No PGA; ADC only) (ve rsion v5a ) Vbat = Vref = 5.0V 500kHz; OSR = 512; NELCONV = 2 f ...

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ADC converter (GDtot = 10) (version v5a) Vbat = Vref = 5.0V 500kHz; OSR = 512; NELCONV = 2MHz; IB_AMP(1:0) = 11; Vinn= sweep = 1201; average on 4 samples ...

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ADC converter (GDtot = 1000) (version v5a) Vbat = Vref = 5.0V 500kHz; OSR = 512; NELCONV = 2MHz; IB_AMP(1:0) = 11; Vinn= sweep = 1201; average on 4 samples ...

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Where V n,outx Typical output noise per Amplifier Symbol over-sample V PGA1 n,out1 V PGA2 n,out2 V PGA3 n,out3 Typical output noise of ZoomingADC preamplifiers ADC only Figure 8.17: Noise measured at the output of the ZoomingADC As one can ...

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Offset error is defined as the output code error for a zero volt input (ideally, output code = 0). The measured offset errors vs. temperature curves for different PGA gains are depicted in the right figure below. The output offset ...

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Temperature [°C] Figure 8.20: Absolute and (b) relative change in quiescent current consumption vs. temperature 850 800 750 700 650 600 550 500 0 500 1000 ...

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Figure 8.22: Power supply rejection ratio (PSRR) Supply GAIN = 1 GAIN = Table 8.9: PSRR ( bits, V 8.14 Frequency Response The incremental ADC of ...

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Normalized Frequency - f *(OSR/f 1.2 1 0.8 0.6 0.4 0 Normalized Frequency - f *(OSR/f Figure 8.23: Frequency response: normalized magnitude vs. frequency for different ...

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Physical description 9.1 LQFP44 package Figure 9.1: LQFP44 package, size in mm. 9.2 PLL-44L package Figure 9.2: PLL-44L package, 34 Data Sheet XE88LC01 Data Acquisition Microcontroller D0202-60 ...

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Die form pin 1 Figure 9.3: XE88LC01 in die: 4.1 x 4.6 mm 9.3.1 Bonding pads location Coordinates start with a point near to the bottom left border (with respect to above picture horizontal vertical. ...

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