XE8806A SEMTECH [Semtech Corporation], XE8806A Datasheet - Page 39

• Manufacturer Part Number: XE8806A
• Description: Ultra Low-Power Low-Voltage
• Manufacturer: SEMTECH [Semtech Corporation]

In assembler code, the sequence to clear the watchdog is:
Only writing Hx0A followed by Hx03 resets the WD. If some other write instruction is done to the RegSysWd
between the writing of the Hx0A and Hx03 values, the watchdog timer will not be cleared.
It is possible to read the status of the watchdog in the RegSysWd register. The watchdog is a 4 bit counter with a
count range between 0 and 7. The system reset is generated when the counter is reaching the value 8.
6.9
At start-up of the circuit, the POR block generates a reset signal during t
after this period (see system chapter). The POR is intended to force the circuit into a correct state at start-up. For
precise monitoring of the supply voltage, the voltage level detector (VLD) has to be used.
Note: 1) The Vbat_sl defines the minimum slope required on VBAT. Correct start-up of the circuit is not guaranteed
if this slope is too slow. In such a case, a delay has to be built using the NRESET pin.
Note: 2) The minimal watchdog timeout period is guaranteed when the internal oscillators are used. In case an
external clock source is used, the watchdog timeout period will be correct in so far the contents of the
RegSysRCTrim1 and RegSysRCTrim2 registers are correct (see clock block documentation for more details).
© Semtech 2006
Symbol
WDtime
Vbat_sl
T
POR
Start-up and watchdog specifications
move AddrRegSysWd, #0x0A
move AddrRegSysWd, #0x03
POR reset duration
Watchdog timeout period
Supply ramp up
Parameter
Table 6. Electrical and timing specifications
Min
0.5
5
2
6-6
Typ
Max
20
POR
V/ms
Unit
. The circuit starts software execution
ms
s
XE8806A/XE8807A
Comments
1
2
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