XE8806A SEMTECH [Semtech Corporation], XE8806A Datasheet - Page 130

• Manufacturer Part Number: XE8806A
• Description: Ultra Low-Power Low-Voltage
• Manufacturer: SEMTECH [Semtech Corporation]

The PWM resolution is always 8 bits when the counters used for the PWM signal generation are not cascaded.
PWM0Size(1:0) and PWM1Size(1:0) in the RegCntConfig2 register are used to set the PWM resolution for the
counters A and B or C and D respectively when they are in cascaded mode. The different possible resolutions in
cascaded mode are shown in Table 17-14. Choosing a 16 bit PWM code which is higher than the maximum value
that can be represented by the number of bits chosen for the resolution results in a PWM output which is always
tied to 1.
The period of the PWM signal is given by the formula:
The duty cycle ratio DCR of the PWM signal is defined as:
DCR can be selected between
DCR in % in function of the RegCntX content(s) is given by the relation:
17.11 Capture function
The 16-bit capture register is provided to facilitate frequency measurements. It provides a safe reading mechanism
for the counters A and B when they are running. When the capture function is active, the processor does not read
anymore the counters A and B directly, but instead reads shadow registers located in the capture block. An
interrupt is generated after a capture condition has been met when the shadow register content is updated. The
capture condition is user defined by selecting either internal capture signal sources derived from the prescaler or
from the external PA(2) or PA(3) ports. Both counters use the same capture condition.
© Semtech 2006
Small PWM code
Large PWM code
Table 17-14: Resolution selection in cascaded PWM mode
2
PwmXsize(1:0)
resolution
100
DCR
11
10
01
00
Figure 17-3: PWM modulation examples
% and 100 %.
=
MIN
Tper
DCR =
⎛
⎜
⎝
100
T
llarge
=
17-9
(
1
2
2
+
resolution
Tper
f
resolution
Th
ckcnt
RegCntX
T
Resolution
lsmall
T
T
16 bits
14 bits
12 bits
10 bits
hlarge
per
)
,
100
⎞
⎟
⎠
T
XE8806A/XE8807A
hsmall
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