MK68564N-04 STMICROELECTRONICS [STMicroelectronics], MK68564N-04 Datasheet - Page 22

• Manufacturer Part Number: MK68564N-04
• Description: SERIAL INPUT OUTPUT
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Figure 12 : Transmit/Receive SDLC/HDLC Message Format.
sage length and bit patterns. The SIO has several
built-in features to handle variable message length.
Detailed information concerning SDLC protocol can
be found in literature on this subject, such as IBM do-
cument GA27-3093.
The SDLC message, called the frame (figure 12), is
opened and closed by flags, which are similar to the
sync characters used in other Synchronous proto-
cols. The SIO handles the transmission and reco-
gnition of the flag characters that mark the beginning
and end of the frame. Note that the SIO can receive
shared-zero flags but cannot transmit them. The 8-
bit address field of a SDLC frame contains the se-
condary station address. The SIO receiver has an
Address Search mode, which recognizes the se-
condary station so that it can accept or reject a
frame.
The control field of the SDLC frame is transparent
to the SIO ; it is simply transferred to the CPU. The
SIO handles the Frame Check sequence in a man-
ner that simplifies the program by incorporating fea-
tures such as initializing the CRC generator to all
ones, resetting the CRC checker when the opening
flag is detected in the receive mode, and sending the
Frame Check/Flag sequence in the transmit mode.
Controller hardware is simplified by automatic zero
insertion and deletion logic, contained in the SIO.
To set up the SIO for SDLC operation, the following
registers need to be initialized : Mode Control Re-
gister, Interrupt Control Register, Receiver Control
Register, Transmitter Control Register, Sync Word
Register 1, and Sync Word Register 2. The Mode
Control Register must be programmed before the o-
ther registers to assure proper operation of the SIO.
The following registers are used to transfer data or
communicate status between the SIO and the CPU
or other bus master when operating in SDLC mode
: Command Register, Status Register 0, Status Re-
gister 1, Data Register, and the Vector Register.
Sync Word Register 1 contains the secondary sta-
tion address, and Sync Word Register 2 stores the
22/46
flag character and must be programmed to
”01111110”.
The SIO provides four I/O lines in SDLC mode that
may be used for modem control, for external inter-
rupts, or as general purpose I/O. The Request To
Send (RTS) and Data Terminal Ready (DTR) pins
are outputs that follow the inverted state of their res-
pective bits in the Transmit Control Register. The
Data Carrier Detect (DCD) and Clear To Send
(CTS) pins are inputs that can be used as auto en-
ables to the receiver and transmitter, respectively. If
External/Status Interrupts are enabled, the DCD
and CTS pins will be monitored for a change of sta-
tus. If these inputs change for a period of time grea-
ter than the minimum specified pulse width, an in-
terrupt will be generated.
In the following discussion, all interrupt modes are
assumed enabled.
SDLC TRANSMIT
Initialization. The SIO is initialized for SDLC mode
by selecting these parameters in the Mode Control
Register : x1 Clock Mode, SDLC Mode, and Sync
Modes Enabled. Parity is normally not used in SDLC
mode, because the transmitter will not add parity to
the flag character or the CRC characters, thus cau-
sing Parity Errors in the receiver. If CRC is to be cal-
culated on the transmitted data, the SDLC-CRC
polynomial must be selected in the Interrupt Control
Register (CRC-16 polynomial in SDLC Mode will
produce unknown results).
After reset (hardware or software), or when the
transmitter is not enabled, the Transmit Data (TxD)
output pin is held High (marking). Under program
control, the Send Break bit in the Transmit Control
Register can be set to a one, forcing the TxD output
to a Low level (spacing), even if the transmitter is not
enabled. The spacing condition will persist until the
Send Break bit is reset to a zero. If the transmit buffer
is empty when the Transmit Enable bit is set to a
one, the transmitter will start sending flag charac-
ters. Continuous flags will be transmitted on the TxD
V000386