MK68564N-04 STMICROELECTRONICS [STMicroelectronics], MK68564N-04 Datasheet - Page 12

• Manufacturer Part Number: MK68564N-04
• Description: SERIAL INPUT OUTPUT
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

nal/status logic latches the current state of all five in-
put conditions, and generates an interrupt. To reini-
tialize the external/status logic to detect another
transition, a Reset External/Status Interrupts
command must be issued. The Break/Abort condi-
tion allows the SIO to generate an interrupt when the
Break/Abort sequence is detected and terminated.
This feature facilitates the proper termination of the
current message, correct initialization of the next
message, and the accurate timing of the Break/A-
bort condition in external logic.
DMA Transfer
The SIO provides two output signals per channel for
connection to a DMA controller ; they are TxRDY
and RxRDY. The outputs are enabled under soft-
ware control by writing to the Interrupt Control Re-
gister. Both outputs will pulse Low for three system
clock cycles when their input conditions are active.
TxRDY will be active when the Transmit Buffer
becomes empty. RxRDY will be active when a char-
acter is available in the Receive Buffer. If a Special
Receive Condition occurs when Interrupt On First
Character Only mode is selected, a receiver inter-
rupt will be generated and RxRDY will not become
active. This will automatically inform the CPU of a
discrepancy in the data transfer.
Figure 7 : Interrupt Structure.
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SELF TEST
When the Loop Mode bit is set in the Command Re-
gister,the receiver shift clock input pin (RxC) and the
receiver data input pin (RxD) are electrically dis-
connected from the internal logic. The transmit data
output pin (TxD) is connected to the internal
receiver data logic, and the transmit shift clock pin
(TxC) is connected to the internal receiver shift clock
logic. All other features of the SIO are unaffected.
BAUD RATE GENERATORS
Each channel in the SIO contains a programmable
baud rate generator (BRG). Each BRG consists of
an 8-bit time constant register, an 8-bit down coun-
ter, a control register, and a flip-flop on the output to
provide a square wave signal out. In addition to the
flip-flop on the output, there is also a flip-flop on the
input clock ; therefore, the maximum output frequen-
cy of the BRG is one-forth of the input clock frequen-
cy. This maximum output frequency occurs when
divide by four mode is selected, and the time
constant register is loaded with the minimum count
of ”01H”. The equation to determine the output fre-
quency is :
Output
Frequency
=
(divide by selected) X (time constant
Input Frequency
value in decimal)
V000380