EP1C4 ALTERA [Altera Corporation], EP1C4 Datasheet - Page 34

• Manufacturer Part Number: EP1C4
• Description: Cyclone FPGA Family Data Sheet
• Manufacturer: ALTERA [Altera Corporation]

Cyclone Device Handbook, Volume 1
Figure 2–20. Read/Write Clock Mode in Simple Dual-Port Mode
Notes to
(1)
(2)
2–28
Preliminary
wraddress[ ]
address[ ]
byteena[ ]
wrclken
wrclock
rdclken
rdclock
All registers shown except the rden register have asynchronous clear ports.
Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
data[ ]
wren
rden
Figure
6 LAB Row
Clocks
6
2–20:
Read/Write Clock Mode
The M4K memory blocks implement read/write clock mode for simple
dual-port memory. You can use up to two clocks in this mode. The write
clock controls the block's data inputs, wraddress, and wren. The read
clock controls the data output, rdaddress, and rden. The memory
blocks support independent clock enables for each clock and
asynchronous clear signals for the read- and write-side registers.
Figure 2–20
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
shows a memory block in read/write clock mode.
Q
Q
Q
Q
Q
Q
Generator
Pulse
Write
Data In
Read Address
Write Address
Byte Enable
Read Enable
Write Enable
Notes
Memory Block
1,024 × 4
2,048 × 2
4,096 × 1
Data Out
256 × 16
512 × 8
(1),
(2)
D
ENA
Q
Altera Corporation
January 2007
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