EP1C4 ALTERA [Altera Corporation], EP1C4 Datasheet - Page 23
EP1C4
Manufacturer Part Number
EP1C4
Description
Cyclone FPGA Family Data Sheet
Manufacturer
ALTERA [Altera Corporation]
Datasheet
1.EP1C4.pdf
(104 pages)
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Altera Corporation
January 2007
LUT Chain
Register Chain
Local Interconnect
Direct Link
Interconnect
R4 Interconnect
C4 Interconnect
LE
M4K RAM Block
PLL
Column IOE
Row IOE
Table 2–2. Cyclone Device Routing Scheme
Source
v
All embedded blocks communicate with the logic array similar to LAB-
to-LAB interfaces. Each block (i.e., M4K memory or PLL) connects to row
and column interconnects and has local interconnect regions driven by
row and column interconnects. These blocks also have direct link
interconnects for fast connections to and from a neighboring LAB.
Table 2–2
v
v
v
v
v
v
shows the Cyclone device's routing scheme.
v
v
v
v
v
v
v
v
v
v
Destination
v
v
v
v
v
v
v
v
v
v
v
MultiTrack Interconnect
v
v
Preliminary
v
2–17