AD14160KB-4 AD [Analog Devices], AD14160KB-4 Datasheet - Page 28

• Manufacturer Part Number: AD14160KB-4
• Description: Quad-SHARC DSP Multiprocessor Family
• Manufacturer: AD [Analog Devices]

Parameter
Timing Requirements:
t
t
t
t
t
t
t
t
Switching Characteristics:
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
W = (number of wait states specified in WAIT register)
HI = t
NOTES
1
2
3
4
AD14160/AD14160L
DMA Handshake
These specifications describe the three DMA handshake modes.
In all three modes DMAR is used to initiate transfers. For hand-
shake mode, DMAG controls the latching or enabling of data
externally. For external handshake mode, the data transfer is
controlled by the ADDR
ACK, and DMAG signals. For Paced Master mode, the data
Only required for recognition in the current cycle.
t
t
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
SDRLC
SDRHC
WDR
SDATDGL
HDATIDG
DATDRH
DMARLL
DMARH
DDGL
WDGH
WDGL
HDGC
VDATDGH
DATRDGH
DGWRF
DGWRH
DGWRR
DGRDF
DRDGH
DGRDR
DGWR
DADGH
DDGHA
data can be driven t
n equals the number of extra cycles that the access is prolonged.
SDATDGL
VDATDGH
CK
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the
is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then t
DMARx Low Setup Before CLKIN
DMARx High Setup Before CLKIN
DMARx Width Low (Nonsynchronous)
Data Setup After DMAGx Low
Data Hold After DMAGx High
Data Valid After DMAGx High
DMAGx Low Edge to Low Edge
DMAGx Width High
DMAGx Low Delay After CLKIN
DMAGx High Width
DMAGx Low Width
DMAGx High Delay After CLKIN
Data Valid Before DMAGx High
Data Disable After DMAGx High
WR Low Before DMAGx Low
DMAGx Low Before WR High
WR High Before DMAGx High
RD Low Before DMAGx Low
RD Low Before DMAGx High
RD High Before DMAGx High
DMAGx High to WR, RD, DMAGx Low
Address/Select Valid to DMAGx High
Address/Select Hold After DMAGx High
DATDRH
after DMARx is brought high.
31-0
, RD, WR, SW, PAGE, MS
2
2
3
4
1
1
t
CK
.
Min
5.5
5.5
6
2.5
23 + 7DT/8
6
9 + DT/4
6 + 3DT/8
12 + 5DT/8
–2 – DT/8
7 + 9DT/16
–0.5
–0.5
9.5 + 5DT/8 + W
0.5 + DT/16
–0.5
10.5 + 9DT/16 + W
–0.5
5 + 3DT/8 + HI
16 + DT
–1.5
3-0
,
40 MHz–5 V
–28–
transfer is controlled by ADDR
(not DMAG). For Paced Master mode, the “Memory Read–Bus
Master”, “Memory Write–Bus Master”, and “Synchronous
Read/Write–Bus Master” timing specifications for ADDR
RD, WR, MS
Max
9 + 5DT/8
15 + 7DT/8
16 + DT/4
7 – DT/8
8
2.5
3.5 + DT/16
2.5
3.5
3-0
, SW, PAGE, DATA
Min
5.5
5.5
6
2.5
23 + 7DT/8
6
9 + DT/4
6 + 3DT/8
12 + 5DT/8
–2 – DT/8
7 + 9DT/16
–0.5
–0.5
9.5 + 5DT/8 + W
0.5 + DT/16
–0.5
10.5 + 9DT/16 + W
–0.5
5 + 3DT/8 + HI
16 + DT
–1.5
40 MHz–3.3 V
VDATDGH
31-0
, RD, WR, MS
47-0
= 7 + 9DT/16 + (n
, and ACK also apply.
Max
9 + 5DT/8
15 + 7DT/8
16 + DT/4
7 – DT/8
8
2.5
3.5 + DT/16
2.5
3.5
3-0
, and ACK
t
CK
REV. A
31-0
) where
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
,