AD14160KB-4 AD [Analog Devices], AD14160KB-4 Datasheet - Page 19

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AD14160KB-4

Manufacturer Part Number
AD14160KB-4
Description
Quad-SHARC DSP Multiprocessor Family
Manufacturer
AD [Analog Devices]
Datasheet
REV. A
Memory Write—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the AD14160/
AD14160L is the bus master accessing external memory space.
Parameter
Timing Requirements:
t
t
Switching Characteristics:
t
t
t
t
t
t
t
t
t
t
W = (number of wait states specified in WAIT register)
H = t
I = t
NOTES
1
2
3
ACK Delay/Setup: User must meet t
For MSx, SW, BMS, the falling edge is referenced.
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
DAAK
DSAK
DAWH
DAWL
WW
DDWH
DWHA
DATRWH
WWR
DDWR
WDE
SADADC
CK
CK
(if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
(if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
ACK Delay from Address, Selects
ACK Delay from WR Low
Address, Selects to WR Deasserted
Address, Selects to WR Low
WR Pulsewidth
Data Setup Before WR High
Address Hold After WR Deasserted
Data Disable After WR Deasserted
WR High to WR, RD, DMAGx Low
Data Disable Before WR or RD Low
WR Low to Data Enabled
Address, Selects to ADRCLK High
RD , DMAG
ADDRESS
MSx , SW
ADRCLK
DATA
(OUT)
BMS
ACK
WR
DAAK
t
SADADC
or t
t
DAWL
1
DSAK
2
t
or synchronous specification t
DAAK
1, 2
3
2
Figure 15. Memory Write—Bus Master
2
t
CK
.
Min
16 + 15DT/16 + W
2 + 3DT/8
12 + 9DT/16 + W
6 + DT/2 + W
0 + DT/16 + H
0.5 + DT/16 + H
7.5 + 7DT/16 + H
4 + 3DT/8 + I
–1.5 + DT/16
–0.5 + DT/4
t
DSAK
t
WDE
40 MHz–5 V
t
DAWH
–19–
SACKC
t
These switching characteristics also apply for bus master syn-
chronous read/write timing (see Synchronous Read/Write—Bus
Master). If these timing requirements are met, the synchronous
read/write timing can be ignored (and vice versa).
WW
Max
13 + 7DT/8 + W
7 + DT/2 + W
7 + DT/16 + H
.
t
DDWH
Min
16 + 15DT/16 + W
2 + 3DT/8
12 + 9DT/16 + W
6 + DT/2 + W
0 + DT/16 + H
0.5 + DT/16 + H
7.5 + 7DT/16 + H
4 + 3DT/8 + I
–1.5 + DT/16
–0.5 + DT/4
40 MHz–3.3 V
AD14160/AD14160L
t
DATRWH
t
DWHA
t
WWR
Max
13 + 7DT/8 + W
7 + DT/2 + W
7 + DT/16 + H
t
DDWR
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
ns

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