SAF7115ET NXP [NXP Semiconductors], SAF7115ET Datasheet - Page 12

• Manufacturer Part Number: SAF7115ET
• Description: Multistandard video decoder with super-adaptive comb filter,
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
Table 4.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
SAF7115_1
Product data sheet
Symbol
XRDY
XRH
XRV
XTRI
Host port (H-port)
HPD7
HPD6
HPD5
HPD4
HPD3
HPD2
HPD1
HPD0
A = analog, I = input, O = output, P = power, st = strapping, pu = pull-up, pd = pull-down, od = open-drain.
For CGC1 and CGC2.
For analog inputs AI1x.
For analog inputs AI2x.
For normal operation connect pins AI1D and AI2D to ground through a capacitor. In principle both analog input stages can operate in
differential mode, too, depending on the application. This may be interesting for differential video (CVBS). Please contact NXP for more
information.
This contains information about actual system clock frequency, field rate, odd/even sequence, decoder status, subcarrier phase and
frequency and PAL sequence (according to RTC level 3.1, refer to external document RTC Functional Specification for details), can be
strapped to supply through a 3.3 k resistor to change the default I
pull-down) to 40h and 41h.
According to the IEEE1149.b1-1994 standard pins TDI and TMS are input pins with an internal pull-up transistor and TDO is a 3-state
output pin. Pins TCK and TRST_N are also built with internal pull-up.
This pin provides easy initialization of BST circuitry. Pin TRST_N can be used to force the Test Access Port (TAP) controller to the
test-logic-reset state (normal operation) at once.
Pin description
Pin
HTQFP100
96
92
91
80
64
65
66
67
69
70
71
72
…continued
TFBGA160
A4
A6
B6
A12
G13
G14
F13
F14
E14
D13
D14
C13
Type
O
I/O
I/O
I/pd
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Rev. 01 — 15 October 2008
[1]
Description
task flag or read signal from scaler, controlled by bit XRQT
(subaddress 83h)
horizontal reference I/O expansion-port: in 10-bit video output
mode: this signal represents the video bit 1
vertical reference I/O expansion-port: in 10-bit video output mode:
this signal represents the video bit 0 (LSB)
X-port output control signal, affects all X-port pins (XPD[7:0],
XRH, XRV, XDQ and XCLK) enable and active polarity is under
software control (bits XPE in subaddress 83h)
MSB of host port data I/O, carries CbCr chrominance information
in 16-bit video I/O modes
MSB
information in 16-bit video I/O modes
MSB
information in 16-bit video I/O modes
MSB
information in 16-bit video I/O modes
MSB
information in 16-bit video I/O modes
MSB
information in 16-bit video I/O modes
MSB
information in 16-bit video I/O modes
LSB of host port data I/O, carries CbCr chrominance information
in 16-bit video I/O modes
2
C-bus read and write addresses from 42h and 43h (internal
1 of host port data I/O, carries CbCr chrominance
2 of host port data I/O, carries CbCr chrominance
3 of host port data I/O, carries CbCr chrominance
4 of host port data I/O, carries CbCr chrominance
5 of host port data I/O, carries CbCr chrominance
6 of host port data I/O, carries CbCr chrominance
Multistandard video decoder
SAF7115
© NXP B.V. 2008. All rights reserved.
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