ADSP-BF606 AD [Analog Devices], ADSP-BF606 Datasheet - Page 13

• Manufacturer Part Number: ADSP-BF606
• Description: Blackfin Dual Core
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
The ACM synchronizes the ADC conversion process, generat-
ing the ADC controls, the ADC conversion start signal, and
other signals. The actual data acquisition from the ADC is done
by a peripheral such as a SPORT or a SPI.
The processor interfaces directly to many ADCs without any
glue logic required.
General-Purpose Counters
A 32-bit counter is provided that can operate in general-pur-
pose up/down count modes and can sense 2-bit quadrature or
binary codes as typically emitted by industrial drives or manual
thumbwheels. Count direction is either controlled by a level-
sensitive input pin or by two edge detectors.
A third counter input can provide flexible zero marker support
and can alternatively be used to input the push-button signal of
thumb wheels. All three pins have a programmable debouncing
circuit.
Internal signals forwarded to each general-purpose timer enable
these timers to measure the intervals between count events.
Boundary registers enable auto-zero operation or simple system
warning by interrupts when programmable count values are
exceeded.
Serial Peripheral Interface (SPI) Ports
The processors have two SPI-compatible ports that allow the
processor to communicate with multiple SPI-compatible
devices.
In its simplest mode, the SPI interface uses three pins for trans-
ferring data: two data pins (Master Output-Slave Input, MOSI,
and Master Input-Slave Output, MISO) and a clock pin (serial
clock, SCK). An SPI chip select input pin (SPISS) lets other SPI
devices select the processor, and seven SPI chip select output
pins (SPISEL7–1) let the processor select other SPI devices. The
SPI select pins are reconfigured general-purpose I/O pins. Using
these pins, the SPI port provides a full-duplex, synchronous
serial interface, which supports both master/slave modes and
multimaster environments.
The SPI port’s baud rate and clock phase/polarities are pro-
grammable, and it has integrated DMA channels for both
transmit and receive data streams.
UART Ports
The processors provide two full-duplex universal asynchronous
receiver/transmitter (UART) ports, which are fully compatible
with PC-standard UARTs. Each UART port provides a simpli-
fied UART interface to other peripherals or hosts, supporting
full-duplex, DMA-supported, asynchronous transfers of serial
data. A UART port includes support for five to eight data bits,
and none, even, or odd parity. Optionally, an additional address
bit can be transferred to interrupt only addressed nodes in
multi-drop bus (MDB) systems. A frame is terminates by one,
one and a half, two or two and a half stop bits.
The UART ports support automatic hardware flow control
through the Clear To Send (CTS) input and Request To Send
(RTS) output with programmable assertion FIFO levels.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Rev. PrD | Page 13 of 44 | March 2012
To help support the Local Interconnect Network (LIN) proto-
cols, a special command causes the transmitter to queue a break
command of programmable bit length into the transmit buffer.
Similarly, the number of stop bits can be extended by a pro-
grammable inter-frame space.
The capabilities of the UARTs are further extended with sup-
port for the Infrared Data Association (IrDA®) serial infrared
physical layer link specification (SIR) protocol.
TWI Controller Interface
The processors include a 2-wire interface (TWI) module for
providing a simple exchange method of control data between
multiple devices. The TWI module is compatible with the
widely used I
capabilities of simultaneous master and slave operation and
support for both 7-bit addressing and multimedia data arbitra-
tion. The TWI interface utilizes two pins for transferring clock
(TWI_SCL) and data (TWI_SDA) and supports the protocol at
speeds up to 400k bits/sec. The TWI interface pins are compati-
ble with 5 V logic levels.
Additionally, the TWI module is fully compatible with serial
camera control bus (SCCB) functionality for easier control of
various CMOS camera sensor devices.
Removable Storage Interface (RSI)
The removable storage interface (RSI) controller acts as the host
interface for multimedia cards (MMC), secure digital memory
cards (SD), secure digital input/output cards (SDIO), and CE-
ATA hard disk drives. The following list describes the main fea-
tures of the RSI controller.
Controller Area Network (CAN)
A CAN controller implements the CAN 2.0B (active) protocol.
This protocol is an asynchronous communications protocol
used in both industrial and automotive control systems. The
CAN protocol is well suited for control applications due to its
capability to communicate reliably over a network. This is
because the protocol incorporates CRC checking, message error
tracking, and fault node confinement.
• Support for a single MMC, SD memory, SDIO card or CE-
• Support for 1-bit and 4-bit SD modes
• Support for 1-bit, 4-bit, and 8-bit MMC modes
• Support for 4-bit and 8-bit CE-ATA hard disk drives
• Support for eMMC 4.3 embedded NAND flash devices
• A ten-signal external interface with clock, command, and
• Card interface clock generation from SCLK0
• SDIO interrupt and read wait features
• CE-ATA command completion signal recognition and
ATA hard disk drive
up to eight data lines
disable
2
C bus standard. The TWI module offers the