ADSP-BF606 AD [Analog Devices], ADSP-BF606 Datasheet - Page 12

• Manufacturer Part Number: ADSP-BF606
• Description: Blackfin Dual Core
• Manufacturer: AD [Analog Devices]

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
being reset by software. The programmer initializes the count
value of the timer, enables the appropriate interrupt, then
enables the timer. Thereafter, the software must reload the
counter before it counts to zero from the programmed value.
This protects the system from remaining in an unknown state
where software, which would normally reset the timer, has
stopped running due to an external noise condition or software
error.
After a reset, software can determine if the watchdog was the
source of the hardware reset by interrogating a status bit in the
timer control register, which is set only upon a watchdog gener-
ated reset.
3-Phase PWM Units
The two 3-phase PWM generation units each feature:
Each PWM block integrates a flexible and programmable
3-phase PWM waveform generator that can be programmed to
generate the required switching patterns to drive a 3-phase volt-
age source inverter for ac induction motor (ACIM) or
permanent magnet synchronous motor (PMSM) control. In
addition, the PWM block contains special functions that con-
siderably simplify the generation of the required PWM
switching patterns for control of the electronically commutated
motor (ECM) or brushless dc motor (BDCM). Software can
enable a special mode for switched reluctance motors (SRM).
The eight PWM output signals (per PWM unit) consist of four
high-side drive signals and four low-side drive signals. The
polarity of a generated PWM signal can be set with software, so
that either active HI or active LO PWM patterns can be
produced.
Pulses synchronous to the switching frequency can be generated
internally and output on the PWM_SYNC pin. The PWM unit
can also accept externally generated synchronization pulses
through PWM_SYNC.
Each PWM unit features a dedicated asynchronous shutdown
pin which (when brought low) instantaneously places all six
PWM outputs in the OFF state.
Link Ports
Four DMA-enabled, 8-bit-wide link ports can connect to the
link ports of other DSPs or processors. Link ports are bidirec-
tional ports having eight data lines, an acknowledge line and a
clock line.
• 16-bit center-based PWM generation unit
• Programmable PWM pulse width
• Single/double update modes
• Programmable dead time and switching frequency
• Twos-complement implementation which permits smooth
• Dedicated asynchronous PWM shutdown signal
transition to full ON and full OFF states
Rev. PrD | Page 12 of 44 | March 2012
Serial Ports (SPORTs)
Three synchronous serial ports that provide an inexpensive
interface to a wide variety of digital and mixed-signal peripheral
devices such as Analog Devices’ AD183x family of audio codecs,
ADCs, and DACs. The serial ports are made up of two data
lines, a clock, and frame sync. The data lines can be pro-
grammed to either transmit or receive and each data line has a
dedicated DMA channel.
Serial port data can be automatically transferred to and from
on-chip memory/external memory via dedicated DMA chan-
nels. Each of the serial ports can work in conjunction with
another serial port to provide TDM support. In this configura-
tion, one SPORT provides two transmit signals while the other
SPORT provides the two receive signals. The frame sync and
clock are shared.
Serial ports operate in five modes:
ACM Interface
The ADC control module (ACM) provides an interface that
synchronizes the controls between the processor and an analog-
to-digital converter (ADC). The analog-to-digital conversions
are initiated by the processor, based on external or internal
events.
The ACM allows for flexible scheduling of sampling instants
and provides precise sampling signals to the ADC.
Figure 5
and one of the SPORTs.
• Standard DSP serial mode
• Multichannel (TDM) mode
• I
• Packed I
• Left-justified mode
ADSP-BF60x
ADC
2
S mode
shows how to connect an external ADC to the ACM
SPORTx
Figure 5. ADC, ACM, and SPORT Connections
2
ACM
S mode
Preliminary Technical Data
ACM_A[2:0]
ACM_CLK
SPT_CLK
SPT_AD1
SPT_AD0
ACM_FS
ACM_A3
ACM_A4
SPT_FS
SGL/
ADSCLK
RANGE
D
D
A[2:0]
OUT
OUT
SELECT
SPORT
A
B
MUX