ADSP-21267SKBCZ-X AD [Analog Devices], ADSP-21267SKBCZ-X Datasheet - Page 29

• Manufacturer Part Number: ADSP-21267SKBCZ-X
• Description: Preliminary Technical Data
• Manufacturer: AD [Analog Devices]

Table 24. Serial Ports—Enable and Three-State
1
Table 25. Serial Ports—External Late Frame Sync
1
1
Parameter
Switching Characteristics
t
t
t
Referenced to drive edge.
Parameter
Switching Characteristics
t
t
The t
This figure reflects changes made to support Left-justified Sample Pair mode.
DDTEN
DDTTE
DDTIN
DDTLFSE
DDTENFS
DDTLFSE
and t
DDTENFS
Data Enable from External Transmit SCLK
Data Disable from External Transmit SCLK
Data Enable from Internal Transmit SCLK
Data Delay from Late External Transmit FS or External Receive FS
with MCE = 1, MFD = 0
Data Enable for MCE = 1, MFD = 0
parameters apply to Left-justified Sample Pair as well as DSP serial mode, and MCE = 1, MFD = 0.
DIA_P[20:0]
DIA_P[20:0]
NOTE
SERIAL PORT SIGNALS (SCLK, FS, DXA,/DXB) ARE ROUTED TO THE DAI_P[20:1] PINS USING THE SRU.
THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P[20:1] PINS.
DIA_P[20:0]
DIA_P[20:0]
DIA_P[20:0]
DIA_P[20:0]
(D X A/D X B)
(D X A/D X B)
(SCLK)
(SCLK)
(FS)
(FS)
PRELIMINARY TECHNICAL DATA
1
DRIVE
DRIVE
t
DDTLFSE
t
DDTLFSE
t
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0
SFSE/I
t
Rev. PrA | Page 29 of 44 | January 2004
LATE EXTERNAL TRANSMIT FS
DDTENFS
1
t
Figure 21. External Late Frame Sync
t
SFSE/I
DDTENFS
t
HFSE/I
t
SAMPLE
SAMPLE
HFSE/I
1
1
1
1ST BIT
1ST BIT
t
HDTE/I
t
HDTE/I
DRIVE
DRIVE
t
1
Min
2
-1
Min
0.5
DDTE/I
t
DDTE/I
2ND BIT
2ND BIT
Max
7
Max
7
ADSP-21267
Unit
ns
ns
ns
Unit
ns
ns