ADSP-21267SKBCZ-X AD [Analog Devices], ADSP-21267SKBCZ-X Datasheet - Page 18

• Manufacturer Part Number: ADSP-21267SKBCZ-X
• Description: Preliminary Technical Data
• Manufacturer: AD [Analog Devices]

ADSP-21267
Clock Input
Table 9. Clock Input
1
2
3
Clock Signals
The ADSP-21267 can use an external clock or a crystal. See
CLKIN pin description. The programmer can configure the
ADSP-21267 to use its internal clock generator by connecting
the necessary components to CLKIN and XTAL.
the component connections used for a crystal operating in fun-
Reset
Table 10. Reset
1
Parameter
Timing Requirements
t
t
t
t
t
Applies only for CLKCFG1-0 = 00 and default values for PLL control bits in PMCTL.
Applies only for CLKCFG1-0 = 01 and default values for PLL control bits in PMCTL.
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t
Parameter
Timing Requirements
t
t
Applies after the power-up sequence is complete. At power-up, the processor's internal phase-locked loop requires no more than 100 s while RESET is low, assuming
CK
CKL
CKH
CKRF
CCLK
WRST
SRST
stable VDD and CLKIN (not including start-up time of external clock oscillator).
CLKIN
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4V-2.0V)
CCLK Period
RESET Pulse Width Low
RESET Setup Before CLKIN Low
3
Figure 7. Clock Input
t
CKH
RESET
CLKIN
PRELIMINARY TECHNICAL DATA
t
CK
150 MHz
Min
20
7.5
7.5
6.66
1
t
CKL
1
1
1
Figure 8
Rev. PrA | Page 18 of 44 | January 2004
shows
Max
160
80
80
3
10
Figure 9. Reset
t
WRST
2
2
Min
4t
8
2
CK
Figure 8. 150 MHz or 200 MHz Operation (Fundamental Mode Crystal)
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. CRYSTAL
SELECTION MUST COMPLY WITH CLKCFG1-0 = 10 OR = 01.
200 MHz
Min
15
6
6
5
1
1
CCLK
1
.
C1
CLKIN
t
SRST
Max
Max
160
80
80
3
10
1M
X1
2
2
2
C2
XTAL
Unit
ns
ns
ns
ns
ns
Unit
ns
ns