DSP56156FV40 MOTOROLA [Motorola, Inc], DSP56156FV40 Datasheet - Page 24
DSP56156FV40
Manufacturer Part Number
DSP56156FV40
Description
16-bit Digital Signal Processor
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.DSP56156FV40.pdf
(76 pages)
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24
AC Electrical Characteristics and Timing
Reset, Stop, Wait, Mode Select, and Interrupt Timing
NOTES:
D0-D15
RESET
A0-A15
RESET
A0-A15
PS/DS
PS/DS
CLKO
R/W
R/W
1. Circuit stabilization delay is required during reset when using an external clock in two cases:
2. When using fast interrupts, IRQA or IRQB is defined as level-sensitive, then timings 20 and 21
3. The interrupt instruction fetch is visible on the pins only in Mode 3.
4. The minimum is specified for the duration of an edge triggered IRQA interrupt required to recover
5. Timing #22 is for all IRQx interrupts while timing #23 is only when exiting the Wait state.
6. Timing #22 triggers off T1 in the normal state and off phi1 when exiting the Wait state.
7. The instruction fetch is visible on the pins only in Mode 2 and Mode 3.
BS
BS
apply to prevent multiple interrupt service. To avoid these timing restrictions, the negative edge-trig-
gered mode is recommended when using fast interrupts.
from the Stop state. This is not the minimum required so that the IRQA interrupt is accepted.
• after power-on reset
• when recovering from Stop mode
10
13
Freescale Semiconductor, Inc.
Figure 7 Asynchronous Reset Timing
Figure 8 Synchronous Reset Timing
For More Information On This Product,
DSP56156 Data Sheet
Go to: www.freescale.com
11
14
12
First Fetch
V
IHR
MOTOROLA
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