XCR3256XL-7PQ208I XILINX [Xilinx, Inc], XCR3256XL-7PQ208I Datasheet
XCR3256XL-7PQ208I
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XCR3256XL-7PQ208I Summary of contents
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... Preliminary Product Specification 0 14 Description The XCR3256XL is a 3.3V, 256 macrocell CPLD targeted at power sensitive designs that require leading edge program- mable logic solutions. A total of 16 logic blocks provide 6,000 usable gates. Pin-to-pin propagation delays are 7.5 ns with a maximum system frequency of 140 MHz. ...
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... XCR3256XL 256 Macrocell CPLD 140 120 100 Figure 1: XCR3256XL Typical I Table 1: Typical I vs. Frequency Frequency (MHz) 0 Typical I (mA) 0.02 0. Electrical Characteristics Over Recommended Operating Conditions Symbol Parameter V Output High voltage for 3.3V outputs OH V Output Low voltage for 3.3V outputs ...
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... See Figure 4 for derating. 4. Typical current draw during configuration 3.6V. 5. Output pF. L DS013 (v1.2) May 3, 2000 Preliminary Product Specification -7 Min. Max. - 7.0 (3) - 7.5 - 4.5 2 3 140 - 40 - 9.0 (5) - 9.0 - 8.0 - 9.0 www.xilinx.com 1-800-255-7778 XCR3256XL 256 Macrocell CPLD (1,2) -10 -12 Min. Max. Min. Max. - 9.0 - 10.8 - 10.0 - 12.0 - 5.8 - 6.9 2.5 - 3.0 - 6 4.0 - 5.0 - 6 105 ...
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... XCR3256XL 256 Macrocell CPLD Timing Model The XPLA3 architecture follows a simple timing model that allows deterministic timing in design and redesign. The basic timing model is shown in Figure the XPLA3 CPLD is the ability to have product term inputs into a single macrocell and maintain consistent tim- ing ...
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... Internal logic delay (PLA OR term) LOGI2 Feedback Delays T ZIA delay F Time Adders T Fold-back NAND delay LOGI3 T Universal delay UDA T Slew rate limited delay SLEW DS013 (v1.2) May 3, 2000 Preliminary Product Specification XCR3256XL 256 Macrocell CPLD -7 -10 Min. Max. Min ...
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... XCR3256XL 256 Macrocell CPLD Switching Characteristics 7.5 7.4 7.3 7.2 7.1 7.0 6.9 6.8 6.7 6.6 6.5 6.4 6 Number of Adjacent Outputs Switching Figure 4: Derating Curve for T 6 Component OUT Measurement T POE (High) T POE (Low Note: For T POD Figure 3: AC Load Circuit +3.0V 0V Measurements All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified ...
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... CLK0/IN0 A10 181 CLK1/IN1 D11 182 CLK2/IN2 C11 183 CLK3/IN3 B11 184 *Note: BScan Order for CS280 and PQ208 only. DS013 (v1.2) May 3, 2000 Preliminary Product Specification Table 2: XCR3256XL Pin Descriptions (Continued) Function BScan D0 TQ144 Order D1 106 736 D2 - 732 D3 104 (TDO) 728* ...
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... GND R8 - GND R9 - GND R10 - GND R11 - GND R12 - GND R13 - H0 T13 65 H1 W14 64 *Note: BScan Order for CS280 and PQ208 only. 8 Table 2: XCR3256XL Pin Descriptions (Continued) BScan TQ144 Order Function 77 572 H2 - 568 H3 75 564 H4 74 560 H11 - 556 H12 52 - H13 57 - H14 ...
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... R Table 2: XCR3256XL Pin Descriptions (Continued) Function CS280 PQ208 K14 D10 177 K15 C10 178 L0 G2 140 L1 G1 139 L2 G4 138 L3 H1 137 L4 H3 136 L11 H2 135 L12 J2 133 L13 J3 132 L14 K2 131 L15 K3 130 M0 W10 ...
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... XCR3256XL 256 Macrocell CPLD Ordering Information Example: XCR3256XL -7 PQ 208 C Device Type Speed Options Speed Options -12 pin-to-pin delay -10 pin-to-pin delay -7: 7.5 ns pin-to-pin delay Table 3: XCR3256XL JTAG Pinout by package Type Device XCR3256XL TCK Port Enable 144-pin TQ 89 208-pin PQ 30 ...