XCR3256XL-7TQ144C Xilinx Inc, XCR3256XL-7TQ144C Datasheet

IC CPLD 256MCELL 3.3V HP 144TQFP

XCR3256XL-7TQ144C

Manufacturer Part Number
XCR3256XL-7TQ144C
Description
IC CPLD 256MCELL 3.3V HP 144TQFP
Manufacturer
Xilinx Inc
Series
CoolRunner XPLA3r
Datasheet

Specifications of XCR3256XL-7TQ144C

Programmable Type
In System Programmable (min 1K program/erase cycles)
Delay Time Tpd(1) Max
7.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
16
Number Of Macrocells
256
Number Of Gates
6000
Number Of I /o
120
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
144-TQFP, 144-VQFP
Voltage
3.3V
Memory Type
EEPROM
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of Logic Elements/cells
-

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Quantity:
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Part Number:
XCR3256XL-7TQ144C
Manufacturer:
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Quantity:
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Quantity:
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DS013 (v2.7) March 31, 2006
Features
Table 1: Typical I
DS013 (v2.7) March 31, 2006
Frequency (MHz)
Low power 3.3V 256 macrocell CPLD
7.0 ns pin-to-pin logic delays
System frequencies up to 154 MHz
256 macrocells with 6,000 usable gates
Available in small footprint packages
-
-
-
-
Optimized for 3.3V systems
-
-
-
-
-
-
Advanced system features
-
-
-
-
-
-
-
-
Fast ISP programming times
Port Enable pin for additional I/O
2.7V to 3.6V supply voltage at industrial grade voltage
range
Programmable slew rate control per output
Security bit prevents unauthorized access
Refer to the CoolRunner™ XPLA3 family data sheet
(DS012) for architecture description
Typical I
© 2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
144-pin TQFP (120 user I/O pins)
208-pin PQFP (164 user I/O)
256-ball FBGA (164 user I/O)
280-ball CS BGA (164 user I/O)
Ultra low power operation
Typical Standby Current of 18 μA at 25° C
5V tolerant I/O pins with 3.3V core supply
Advanced 0.35 micron five layer metal EEPROM
process
Fast Zero Power™ (FZP) CMOS design
technology
3.3V PCI electrical specification compatible outputs
(no internal clamp diode on any input or I/O)
In-system programming
Input registers
Predictable timing model
Up to 23 clocks available per function block
Excellent pin retention during design changes
Full IEEE Standard 1149.1 boundary-scan (JTAG)
Four global clocks
Eight product term control terms per function block
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
CC
(mA)
CC
vs. Frequency at V
0.018
0
R
0.98
1
CC
= 3.3V, 25°C
9.69
10
0
0
19.3
20
14
XCR3256XL 256 Macrocell CPLD
Product Specification
Description
The CoolRunner™ XPLA3 XCR3256XL device is a 3.3V,
256 macrocell CPLD targeted at power sensitive designs
that require leading edge programmable logic solutions. A
total of 16 function blocks provide 6,000 usable gates.
Pin-to-pin propagation delays are as fast as 7.0 ns with a
maximum system frequency of 154 MHz.
TotalCMOS Design Technique for Fast
Zero Power
CoolRunner XPLA3 CPLDs offer a TotalCMOS™ solution,
both in process technology and design technique. These
CPLDs employ a cascade of CMOS gates to implement
their sum of products, instead of the traditional sense amp
approach. This CMOS gate implementation allows Xilinx
CPLDs to offer devices that are both high performance and
low power, breaking the paradigm that to have low power,
you must have low performance. Refer to
Table 1
TotalCMOS CPLD (data taken with 16 resetable up/down,
16-bit counters at 3.3V, 25°C).
Figure 1: Typical I
38.1
140
120
100
40
60
40
20
80
0
0
XCR3256XL
showing the I
56.2
20
60
40
CC
CC
73.7
vs. Frequency at V
80
vs. Frequency of our XCR3256XL
60
Frequency (MHz)
80
90.8
100
100
107.3
120
CC
120
Figure 1
= 3.3V, 25°C
140
DS013_01_102302
123.9
140
and
160

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XCR3256XL-7TQ144C Summary of contents

Page 1

... Product Specification 0 14 Description The CoolRunner™ XPLA3 XCR3256XL device is a 3.3V, 256 macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of 16 function blocks provide 6,000 usable gates. Pin-to-pin propagation delays are as fast as 7.0 ns with a maximum system frequency of 154 MHz ...

Page 2

... XCR3256XL 256 Macrocell CPLD DC Electrical Characteristics Over Recommended Operating Conditions Symbol Parameter (2) V Output High voltage OH V Output Low voltage for 3.3V outputs Input leakage current IL I I/O High-Z leakage current IH (7) I Standby current CCSB (4,5) I Dynamic current CC (6) C Input pin capacitance ...

Page 3

... These parameters guaranteed by design and/or characterization, not testing. 5. Typical current draw during configuration 3.6V. 6. Output pF. L DS013 (v2.7) March 31, 2006 Product Specification Parameter (3) (6) ) for recommended operating conditions. www.xilinx.com XCR3256XL 256 Macrocell CPLD -7 -10 Min. Max. Min. Max. Min. - 7 ...

Page 4

... XCR3256XL 256 Macrocell CPLD Internal Timing Parameters Symbol Parameter Buffer Delays T Input buffer delay IN T Fast input buffer delay FIN T Global clock buffer delay GCK T Output buffer delay OUT T Output buffer enable/disable delay EN Internal Register and Combinatorial Delays T Latch transparent delay ...

Page 5

... V Figure 3: AC Load Circuit +3.0V 0V Measurements: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified DS013_04_042800 PD2 www.xilinx.com XCR3256XL 256 Macrocell CPLD Values 390Ω 390Ω Open Closed Closed Open Closed Closed , ...

Page 6

... Table 3: XCR3256XL I/O Pins (Continued) Function Block FT256 CS280 3 164 164 FT256 CS280 3 C16 E18 3 F12 E19 3 D16 F15 3 E14 F17 3 E15 F18 F13 F19 ...

Page 7

... R Table 3: XCR3256XL I/O Pins (Continued) Function Macro- Block cell TQ144 PQ208 DS013 (v2.7) March 31, 2006 Product Specification Table 3: XCR3256XL I/O Pins (Continued) Function FT256 CS280 Block - - K15 M17 8 K14 N16 8 K16 N19 8 K13 N18 8 L15 N17 8 R9 U10 8 N9 T10 8 T10 ...

Page 8

... Table 3: XCR3256XL I/O Pins (Continued) Function FT256 CS280 Block (1) ( ...

Page 9

... R Table 3: XCR3256XL I/O Pins (Continued) Function Macro- Block cell TQ144 PQ208 123 122 121 120 119 100 101 102 118 117 115 114 113 112 111 110 DS013 (v2.7) March 31, 2006 Product Specification Table 3: XCR3256XL I/O Pins (Continued) Function FT256 CS280 ...

Page 10

... XCR3256XL 256 Macrocell CPLD Table 4: XCR3256XL Global, JTAG, Port Enable, Power, and No Connect Pins Pin Type TQ144 IN0 / CLK0 128 IN1 / CLK1 127 IN2 / CLK2 126 IN3 / CLK3 125 TCK 89 TDI 4 TDO 104 TMS 20 (1) PORT_EN 13 Vcc 24, 50, 51, 58, 73, 76, 95, 115, 123, 130, 144 ...

Page 11

... R Device Part Marking and Ordering Combination Information Device Type Package Speed Operating Range Speed Device Ordering and (pin-to-pin Part Marking Number delay) XCR3256XL-7TQ144C 7.5 ns XCR3256XL-7TQG144C 7.5 ns XCR3256XL-7PQ208C 7.5 ns XCR3256XL-7PQG208C 7.5 ns XCR3256XL-7FT256C 7.5 ns XCR3256XL-7CS280C 7.5 ns XCR3256XL-7CSG280C 7.5 ns XCR3256XL-10TQ144C 10 ns XCR3256XL-10TQG144C 10 ns XCR3256XL-10PQ208C ...

Page 12

... XCR3256XL 256 Macrocell CPLD Speed Device Ordering and (pin-to-pin Part Marking Number delay) XCR3256XL-12FT256C 12 ns XCR3256XL-12CS280C 12 ns XCR3256XL-12CSG280C 12 ns XCR3256XL-12TQ144I 12 ns XCR3256XL-12TQG144I 12 ns XCR3256XL-12PQ208I 12 ns XCR3256XL-12PQG208I 12 ns XCR3256XL-12FT256I 12 ns XCR3256XL-12CS280I 12 ns XCR3256XL-12CSG280I 12 ns Notes Commercial 0° to +70° Industrial Warranty Disclaimer THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www ...

Page 13

... PD2 to line 2 from line table. OH and Typical and T specifications. Removed T CCSB APRPW www.xilinx.com XCR3256XL 256 Macrocell CPLD SUF spec. Updated T CONFIG HI to match timing model and software Updated Typical I vs. Freq. and F CC specification. SOL ...

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