XCR3128XL-6CS144C XILINX [Xilinx, Inc], XCR3128XL-6CS144C Datasheet - Page 4

• Manufacturer Part Number: XCR3128XL-6CS144C
• Description: XCR3128XL 128 Macrocell CPLD
• Manufacturer: XILINX [Xilinx, Inc]

XCR3128XL 128 Macrocell CPLD
Internal Timing Parameters
4
Notes:
1.
2.
3.
Buffer Delays
T
T
T
T
T
Internal Register and Combinatorial Delays
T
T
T
T
T
T
T
T
T
T
Feedback Delays
T
Time Adders
T
T
T
Symbol
AOI
OUT
IN
FIN
GCK
EN
LDI
SUI
HI
ECSU
ECHO
COI
RAI
LOGI1
LOGI2
F
LOGI3
UDA
SLEW
These parameters guaranteed by design and/or characterization, not testing.
See XPLA family data sheet (
Contact Xilinx for update on advance specification.
Input buffer delay
Fast Input buffer delay
Global Clock buffer delay
Output buffer delay
Output buffer enable/disable delay
Latch transparent delay
Register setup time
Register hold time
Register clock enable setup time
Register clock enable hold time
Register clock to putput delay
Register async. S/R to output delay
Register async. recovery
Internal logic delay (single p-term)
Internal logic delay (PLA OR term)
ZIA delay
Fold-back NAND delay
Universal delay
Slew rate limited delay
Parameter
DS012
) for timing model.
(1,2)
www.xilinx.com
1-800-255-7778
Min.
1.0
0.3
2.0
3.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Advance
(3)
-6
Max.
1.3
2.3
0.8
2.2
4.2
1.3
1.0
2.5
4.0
2.0
2.5
1.7
6.0
1.7
4.0
-
-
-
-
(3)
Min.
1.0
0.5
2.5
4.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-7
Max.
Preliminary
1.6
3.0
1.0
2.7
5.0
1.6
1.3
2.3
5.0
2.7
3.2
2.1
7.5
2.2
5.0
Preliminary Product Specification
-
-
-
-
DS016 (v1.8) January 8, 2002
Min.
1.2
0.7
3.0
5.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-10
Max.
2.2
3.1
1.3
3.6
5.7
2.0
1.6
2.1
6.0
3.3
4.2
3.0
9.5
2.7
6.0
-
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R