MCP434X MICROCHIP [Microchip Technology], MCP434X Datasheet - Page 34
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MCP434X
Manufacturer Part Number
MCP434X
Description
7/8-Bit Quad SPI Digital POT with Non-Volatile Memory
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.MCP434X.pdf
(80 pages)
MCP434X/436X
4.2.2.1
This register contains 7 status bits. These bits show the
state of the WiperLock bits, the Write Protect bit, and if
an EEPROM write cycle is active. The STATUS register
can
Register 4-1
The STATUS register is placed at Address 05h.
REGISTER 4-1:
DS22233A-page 34
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 8-7
bit 6
bit 5
bit 4
Note 1:
R-1
be
D8:D7
accessed
Requires a High Voltage command to modify the state of this bit (for Non-Volatile devices only). This bit is
Not directly written, but reflects the system state (for this feature).
describes each STATUS register bit.
Status (STATUS) Register
D8:D7: Reserved. Forced to “1”
WL3: WiperLock Status bit for Resistor Network 3 (Refer to Section 5.3 “WiperLock™ Technology”
for further information)
The WiperLock Technology bit (WL3) prevents the Volatile and Non-Volatile Wiper 3 addresses and the
TCON1 register bits R3HW, R3A, R3W, and R3B from being written to. High Voltage commands are
required to enable and disable WiperLock Technology.
1 = Wiper and TCON1 register bits R3HW, R3A, R3W, and R3B of Resistor Network 3 (Pot 3) are
0 = Wiper and TCON1 of Resistor Network 3 (Pot 3) can be modified
WL2: WiperLock Status bit for Resistor Network 2 (Refer to Section 5.3 “WiperLock™ Technology”
for further information)
The WiperLock Technology bit (WL2) prevents the Volatile and Non-Volatile Wiper 2 addresses and the
TCON1 register bits R2HW, R2A, R2W, and R2B from being written to. High Voltage commands are
required to enable and disable WiperLock Technology.
1 = Wiper and TCON1 register bits R2HW, R2A, R2W, and R2B of Resistor Network 2 (Pot 2) are
0 = Wiper and TCON1 of Resistor Network 2 (Pot 2) can be modified
EEWA: EEPROM Write Active Status bit
This bit indicates if the EEPROM Write Cycle is occurring.
1 = An EEPROM Write cycle is currently occurring. Only serial commands to the Volatile memory
0 = An EEPROM Write cycle is NOT currently occurring
Note:
Note:
R-1
“Locked” (Write Protected)
“Locked” (Write Protected)
locations are allowed (addresses 00h, 01h, 04h, and 05h)
STATUS REGISTER
via
The WL3 bit always reflects the result of the last programming cycle to the non-volatile WL3
bit. After a POR/BOR or RESET pin event, the WL3 bit is loaded with the non-volatile WL3
bit value.
The WL0 bit always reflects the result of the last programming cycle to the non-volatile WL0
bit. After a POR/BOR or RESET pin event, the WL0 bit is loaded with the non-volatile WL0
bit value.
W = Writable bit
‘1’ = Bit is set
the
WL3
R-1
READ
(1)
WL2
commands.
R-1
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
EEWA
R-0
WL1
R-x
(1)
x = Bit is unknown
WL0
R-x
© 2009 Microchip Technology Inc.
(1)
R-1
—
WP
R-x
(1)
bit 0