DAC1405D750_11 PHILIPS [NXP Semiconductors], DAC1405D750_11 Datasheet - Page 24

• Manufacturer Part Number: DAC1405D750_11
• Description: Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
• Manufacturer: PHILIPS [NXP Semiconductors]

NXP Semiconductors
DAC1405D750
Product data sheet
10.4 Input clock
10.5 Timing
The DAC1405D750 can operate at the following clock frequencies:
The input clock is LVDS compliant (see
differential sine wave signal (see
The DAC1405D750 can operate at a sampling frequency (f
data rate (f
to the CLK signal. When the internal PLL is bypassed, the SYNC signal is used as a
reference. The input timing in the second case is shown in
Fig 8.
Fig 9.
PLL on: up to 185 MHz in Dual-port mode and up to 370 MHz in Interleaved mode
PLL off: up to 750 MHz
LVDS clock configuration
Interfacing CML to LVDS
data
) up to 185 MHz. When using the internal PLL, the input data is referenced
All information provided in this document is subject to legal disclaimers.
CML
Rev. 4 — 7 June 2011
Z
LVDS
diff = 100 Ω
Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating
Z
Figure
diff
= 100 Ω
1 kΩ
100 nF
100 nF
Figure
9).
V
DDA(1V8)
AGND
CLKINP
CLKINN
100 Ω
1.1 kΩ
2.2 kΩ
8) but it can also be interfaced with CML
55 Ω
55 Ω
CLKINN
CLKINP
100 nF
001aah021
s
DAC1405D750
Figure
) up to 750 Msps with an input
LVDS
10.
001aah020
LVDS
© NXP B.V. 2011. All rights reserved.
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