DAC1006LCWM NSC [National Semiconductor], DAC1006LCWM Datasheet - Page 13

• Manufacturer Part Number: DAC1006LCWM
• Description: uP Compatible, Double-Buffered D to A Converters
• Manufacturer: NSC [National Semiconductor]

6 0 DIGITAL CONTROL DESCRIPTION
The DAC1006 series of products can be used in a wide
variety of operating modes Most of the options are shown
in Table 1 Also shown in this table are the section numbers
of this data sheet where each of the operating modes is
discussed For example if your main interest in interfacing
to a P with an 8-bit data bus you will be directed to Section
6 1 0
The first consideration is ‘‘will the DAC be interfaced to a P
with an 8-bit or a 16-bit data bus or used in the stand-alone
mode ’’ For the 8-bit data bus a second selection is made
on how the 2nd digital data buffer (the DAC Latch) is updat-
ed by a transfer from the 1st digital data buffer (the Input
Latch) Three options are provided 1) an automatic transfer
when the 2nd data byte is written to the DAC 2) a transfer
which is under the control of the P and can include more
than one DAC in a simultaneous transfer or 3) a transfer
which is under the control of external logic Further the data
format can be either left justified or right justified
When interfacing to a
selections are available 1) operating the DAC with a single
digital data buffer (the transfer of one DAC does not have to
be synchronized with any other DACs in the system) or
Data Bus
8-Bit Data Bus (6 1 0)
16-Bit Data Bus (6 3 0)
Stand Alone (6 4 0)
Left Justified (6 1 1)
Operating Mode
P with a 16-bit data bus only two
Section
FIGURE 14 Voltage Switching with a Bipolar Output Voltage
6 2 1
6 3 1
6 4 1
Automatic Transfer
Single Buffered
Single Buffered
Figure No
16
17
17
Table 1
13
Section
6 2 2
6 3 2
6 4 2
2) operating with a double digital data buffer for simulta-
neous transfer or updating of more than one DAC
For operating without a P in the stand alone mode three
options are provided 1) using only a single digital data buff-
er 2) using both digital data buffers
3) allowing the input digital data to ‘‘flow through’’ to provide
the analog output without the use of any data latches
To reduce the required reading only the applicable sections
of 6 1 through 6 4 need be considered
6 1 Interfacing to an 8-Bit Data Bus
Transferring 10 bits of data over an 8-bit bus requires two
write cycles and provides four possible combinations which
depend upon two basic data format and protocol decisions
1 Is the data to be left justified (considered as fractional
2 Which byte will be transferred first the most significant
P Control Transfer
binary data with the binary point to the left) or right justi-
fied (considered as binary weighted data with the binary
point to the right)
byte (MS byte) or the least significant byte (LS byte)
Double Buffered
Double Buffered
Figure No
16
17
17
Section
6 2 3
External Transfer
Not Applicable
‘‘double buffered ’’ or
Flow Through
Flow Through
NA
Figure No
TL H 5688-15
16