DAC1006LCWM NSC [National Semiconductor], DAC1006LCWM Datasheet

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DAC1006LCWM

Manufacturer Part Number
DAC1006LCWM
Description
uP Compatible, Double-Buffered D to A Converters
Manufacturer
NSC [National Semiconductor]
Datasheet
C 1995 National Semiconductor Corporation
DAC1006 DAC1007 DAC1008 P Compatible
Double-Buffered D to A Converters
General Description
The DAC1006 7 8 are advanced CMOS Si-Cr 10- 9- and
8-bit accurate multiplying DACs which are designed to inter-
face directly with the 8080 8048 8085 Z-80 and other pop-
ular microprocessors These DACs appear as a memory lo-
cation or an I O port to the
needed
These devices combined with an external amplifier and
voltage reference can be used as standard D A converters
and they are very attractive for multiplying applications
(such as digitally controlled gain blocks) since their linearity
error is essentially independent of the voltage reference
They become equally attractive in audio signal processing
equipment as audio gain controls or as programmable at-
tenuators which marry high quality audio signal processing
to digitally based systems under microprocessor control
All of these DACs are double buffered They can load all 10
bits or two 8-bit bytes and the data format is left justified
The analog section of these DACs is essentially the same
as that of the DAC1020
The DAC1006 series are the 10-bit members of a family of
microprocessor-compatible DAC’s (MICRO-DAC
applications requiring other resolutions the DAC0830 series
(8 bits) and the DAC1208 and DAC1230 (12 bits) are avail-
able alternatives
MICRO-DAC
Typical Application
DAC1006
DAC1007
DAC1008
TM
Part
and BI-FET
TM
are trademarks of National Semiconductor Corp
Accuracy
(bits)
10
9
8
TL H 5688
P and no interfacing logic is
Pin
20
Description
For left-
justified
data
TM
DAC1006 1007 1008
’s) For
Features
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Key Specifications
Y
Y
Y
Y
Y
Y
Uses easy to adjust END POINT specs NOT BEST
STRAIGHT LINE FIT
Low power consumption
Direct interface to all popular microprocessors
Integrated thin film on CMOS structure
Double-buffered single-buffered or flow through digital
data inputs
Loads two 8-bit bytes or a single 10-bit word
Logic inputs which meet TTL voltage level specs (1 4V
logic threshold)
Works with
tion
Operates STAND ALONE (without P) if desired
Available in 0 3 standard 20-pin package
Differential non-linearity selection available as special
order
Output Current Settling Time
Resolution
Linearity
Gain Tempco
Low Power Dissipation
(including ladder)
Single Power Supply
NOTE FOR DETAILS OF BUS
CONNECTION SEE SECTION 6 0
g
10V reference full 4-quadrant multiplica-
TL H 5688 – 1
(guaranteed over temp )
b
RRD-B30M115 Printed in U S A
0 0003% of FS C
10 9 and 8 bits
January 1995
5 to 15 V
20 mW
500 ns
10 bits
DC

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DAC1006LCWM Summary of contents

Page 1

DAC1006 DAC1007 DAC1008 P Compatible Double-Buffered Converters General Description The DAC1006 7 8 are advanced CMOS Si-Cr 10- 9- and 8-bit accurate multiplying DACs which are designed to inter- face directly with the 8080 8048 8085 Z-80 ...

Page 2

Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage ( Voltage at Any Digital Input Voltage at V Input REF Storage Temperature Range ...

Page 3

Electrical Characteristics Tested and Parameter Conditions Output Leakage MIN MAX Current I All data inputs OUT1 latched low I All data inputs ...

Page 4

Switching Waveforms Typical Performance Characteristics Errors vs Supply Voltage Control Setup Time t CS Digital Threshold vs Supply Voltage TL H 5688 – 2 Errors vs Temperature Write Width t Data Setup Time t Data Hold Time t DS Digital ...

Page 5

Block and Connection Diagrams DAC1006 1007 1008 (20-Pin Parts) DAC1006 1007 1008 Simple Hookup for a ‘‘Quick Look’’ A TOTAL OF 10 INPUT SWITCHES 1K RESISTORS Notes 1 For V 10 240 V the output voltage steps are approximately 10 ...

Page 6

DEFINITION OF PACKAGE PINOUTS 1 1 Control Signals (All control signals are level actuated ) CS Chip Select active low it will enable WR WR Write The active low WR is used to load the digital data bits ...

Page 7

Settling Time Settling time is the time required from a code transition until the DAC output reaches within the final output value Full-scale settling time requires a zero to full-scale or full-scale to zero output change Full-Scale Error Full scale ...

Page 8

Op Amp Bias Current Input Leads The op amp bias current (I ) CAN CAUSE DC ERRORS BI- B FET TM op amps have very low bias current and therefore the error introduced is negligible BI-FET op amps ...

Page 9

Figure 4 where the sign of the reference voltage has been changed to provide a positive output voltage Note that the output current I now flows through the R OUT1 pin Providing a Bipolar Output ...

Page 10

Analog Operation in the Voltage Switching Mode Some useful application circuits result if the R-2R ladder is operated in the voltage switching mode There are two very important things to remember when using the DAC in the voltage ...

Page 11

FIGURE 10 Providing a Bipolar Output Voltage with a Single Op Amp FIGURE 11 Increasing the Output Voltage Swing The output voltage swing can be expanded by adding 2 resistors to Figure 10 as shown in Figure 11 These added ...

Page 12

Current Switching with Bipolar Output Voltage The circuit of Figure 12 shows the 3 adjustments needed The first step is to set all of the digital inputs LOW (to force and then trim ‘‘zero ...

Page 13

FIGURE 14 Voltage Switching with a Bipolar Output Voltage 6 0 DIGITAL CONTROL DESCRIPTION The DAC1006 series of products can be used in a wide variety of operating modes Most of the options are shown in Table 1 Also shown ...

Page 14

These data possibilities are shown in Figure 15 Note that the justification of data depends on how the 10-bit data word is located within the 16-bit data source (CPU) register In either case there is a surplus of 6 bits ...

Page 15

Automatic Transfer This makes use of a double byte (double precision) write The first byte (8 bits) is strobed into the input latch and the second byte causes a simultaneous strobe of the two re- maining bits ...

Page 16

FIGURE 17 Input Connections and Logic for DAC1006 1007 1008 with 16-Bit Data Bus Three operating modes are possible flow through single buffered or double buffered The timing diagrams for these are shown below Single Buffered DAC1006 ...

Page 17

MICROPROCESSOR INTERFACE The logic functions of the DAC1006 family have been ori- ented towards an ease of interface with all popular Ps The following sections discuss in detail a few useful interface schemes 7 1 DAC1001 1 2 ...

Page 18

DAC (with regard to left justified data) and the implementation of the PUSH instruction which will output the higher order byte of the register pair (i e register B of the BC pair) first The DAC ...

Page 19

FIGURE 20 Isolating Data Bus from DAC Circuitry to Eliminate Digital Noise Coupling FIGURE 21 Digitally Controlled Amplifier Attenuator 7 4 Digitally Controlled Amplifier Attenuator An unusual application of the DAC Figure 21 applies the input voltage via the on-chip ...

Page 20

... FIGURE 22 Digital to Synchro Converter Ordering Information For Left Justified Data Accuracy 0 05% (10-bit) 0 10% (9-bit) 0 20% (8-bit) Package Outline 20-pin package Temperature Range DAC1006LCN DAC1006LCWM DAC1007LCN DAC1008LCN N20A M20B 5688– 27 ...

Page 21

... Physical Dimensions inches (millimeters) Order Number DAC1006LCWM NS Package Number M20B 21 ...

Page 22

Physical Dimensions inches (millimeters) (Continued) Order Number DAC1006LCN DAC1007LCN or DAC1008LCN LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL ...

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