AD5420BCPZ AD [Analog Devices], AD5420BCPZ Datasheet - Page 24

• Manufacturer Part Number: AD5420BCPZ
• Description: Single Channel, 16-Bit, Serial Input, Current Source DAC
• Manufacturer: AD [Analog Devices]

AD5420
DIGITAL SLEW RATE CONTROL
The Slew Rate Control feature of the AD5420 allows the user to
control the rate at which the output current changes. With the
slew rate control feature disabled the output currrent will
change at a rate limited by the output drive circuitry and the
attached load. If the user wishes to reduce the slew rate this can
be achieved by enabling the slew rate control feature.With the
feature enabled via the SREN bit of the CONTROL register, (See
Table 12) the output, instead of slewing directly between two
values, will step digitally at a rate defined by two parameters
accessible via the CONTROL register as shown in Table 12. The
parameters are SR CLOCK and SR STEP. SR CLOCK defines
the rate at which the digital slew will be updated, e.g. if the
selected update rate is 1MHz the output will update every 1µs,
SR STEP defines by how much the output value will change at
each update. Together both parameters define the rate of change
of the output current.Table 19 and Table 20 outline the range of
values for both the SR CLOCK and SR STEP parameters.
Table 19. Slew Rate Update Clock Options
SR CLOCK
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Update Clock Frequency (Hz)
1000000
500000
333333
250000
200000
100000
50000
33333
25000
20000
12500
10000
8333
6666
5000
3921
Rev. PrD | Page 24 of 29
Table 20. Slew Rate Step Size Options
The following equation describes the slew rate as a function of
the step size, the update clock frequency and the LSB size.
Where:
Slew Rate is expressed in A/µs
LSBSize = Fullscale Range / 65536
When the slew rate control feature is enabled, all output
changes will change at the programmed slew rate, i.e. if the
CLEAR pin is asserted the output will slew to the clear value at
the programmed slew rate. The output can be halted at its
current value with a write to the CONTROL register. To avoid
halting the output slew, the SLEW ACTIVE bit can be used to
check that the slew has completed before writing to the AD5420
registers. See Table 17.
I
Two capacitors may be placed between the pins CAP1, CAP2
and AV
the current output circuitry reducing the bandwidth and the
rate of change of the output current.
SlewRate
OUT
FILTERING CAPACITORS
DD
as shown in Figure 37. The capacitors form a filter on
=
SR STEP
StepSize
000
001
010
011
100
101
110
111
AD5420
Figure 37. I
Preliminary Technical Data
AV
×
GND
UpdateCloc
DD
OUT
CAP2
CAP1
Filtering Capacitors
I
OUT
AV
1×
DD
10
kFrequency
6
Step Size (LSBs)
C
1
128
C
16
32
64
1
2
4
8
2
×
LSBSize