AD5420BCPZ AD [Analog Devices], AD5420BCPZ Datasheet - Page 19

• Manufacturer Part Number: AD5420BCPZ
• Description: Single Channel, 16-Bit, Serial Input, Current Source DAC
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
Table 7. Input Shift Register Format
MSB
D23
Table 8. Control Word Functions
Address
Word
00000000
00000001
00000010
01010101
01010110
Standalone Operation
The serial interface works with both a continuous and noncon-
tinuous serial clock. A continuous SCLK source can only be
used if LATCH is taken high after the correct number of data
bits have been clocked in. In gated clock mode, a burst clock
containing the exact number of clock cycles must be used, and
LATCH must be taken high after the final clock to latch the
data. The first rising edge of SCLK that clocks in the MSB of the
dataword marks the beginning ot the write cycle. Exactly 24
rising clock edges must be applied to SCLK before LATCH is
brought high. If LATCH is brought high before the 24
SCLK edge, the data written will be invalid. If more than 24
rising SCLK edges are applied before LATCH is brought high,
the input data will also be invalid.
D22
D21
DATA Register
CONTROL Register
Function
No Operation (NOP)
Readback register value as per Read Address
(See Table 10)
RESET Register
ADDRESS WORD
D20
D19
D18
D17
D16
D15
th
rising
D14
Rev. PrD | Page 19 of 29
D13
D12
D11
CONTROLLER
SERIAL CLOCK
CONTROL OUT
D10
DATA IN
DATA OUT
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 35. Daisy Chaining the AD5420
D9
DATA WORD
D8
D7
D6
D5
SDIN
SCLK
LATCH
SCLK
LATCH
SCLK
LATCH
D4
AD5420*
AD5420*
AD5420*
SDIN
SDIN
SDO
SDO
SDO
D3
AD5420
D2
D1
LSB
D0