AD5420BCPZ AD [Analog Devices], AD5420BCPZ Datasheet - Page 20

• Manufacturer Part Number: AD5420BCPZ
• Description: Single Channel, 16-Bit, Serial Input, Current Source DAC
• Manufacturer: AD [Analog Devices]

AD5420
Daisy-Chain Operation
For systems that contain several devices, the SDO pin can be
used to daisy chain several devices together as shown in Figure
35. This daisy-chain mode can be useful in system diagnostics
and in reducing the number of serial interface lines. Daisychain
mode is enabled by setting the DCEN bit of the CONTROL 1
register. The first rising edge of SCLK that clocks in the MSB of
the dataword marks the beginning of the write cycle. SCLK is
continuously applied to the input shift register. If more than 24
clock pulses are applied, the data ripples out of the shift register
and appears on the SDO line. This data is clocked out on the
falling edge of SCLK and is valid on the next rising edge. By
connecting the SDO of the first device to the SDIN input of the
next device in the chain, a multidevice interface is constructed.
Each device in the system requires 24 clock pulses. Therefore,
the total number of clock cycles must equal 24 × N , where N is
the total number of AD5420 devices in the chain. When the
serial transfer to all devices is complete, LATCH is taken high.
This latches the input data in each device in the daisy chain.
The serial clock can be a continuous or a gated clock.
A continuous SCLK source can only be used if LATCH is taken
high after the correct number of clock cycles. In gated clock
Table 9. Input Shift Register Contents for a read operation
MSB
D23
0
Table 10. Read Address Decoding
Read Address
D22
0
00
01
10
D21
0
D20
0
D19
0
Function
Read Status Register
Read Data Register
Read Control Register
D18
0
D17
1
D16
0
D15
X
D14
X
Rev. PrD | Page 20 of 29
D13
X
D12
X
mode, a burst clock containing the exact number of clock cycles
must be used, and LATCH must be taken high after the final
clock to latch the data. See Figure 4 for a timing diagram.
Readback Operation
Readback mode is invoked by setting the control word and read
address as shown in Table 9 and Table 10 when writing to the
input register. The next write to the AD5420 should be a NOP
command which will clock out the data from the previously
addressed register as shown in Figure 3.
By default the SDO pin is disabled, after having addressed the
AD5420 for a read operation, a rising edge on LATCH will
enable the SDO pin in anticipation of data being clocked out,
after the data has been clocked out on SDO, a rising edge on
LATCH will disable (tri-state) the SDO pin once again.
To read back the data register for example, the following
sequence should be implemented:
1.
2.
D11
X
Write 0x020001 to the AD5420 input register. This
configures the part for read mode with the data register
selected.
Follow this with a second write, a NOP condition, 0x000000
During this write, the data from the register is clocked out
on the SDO line.
D10
X
D9
X
D8
X
Preliminary Technical Data
D7
X
D6
X
D5
X
D4
X
D3
X
D2
X
D1
Read
Address
LSB
D0