PCA9635PW/Q900 NXP [NXP Semiconductors], PCA9635PW/Q900 Datasheet

PCA9635PW/Q900

Manufacturer Part Number

PCA9635PW/Q900

Description

16-bit Fm+ I2C-bus LED driver

Manufacturer

NXP [NXP Semiconductors]

Datasheet

1.PCA9635PWQ900.pdf (35 pages)

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1. General description

The PCA9635 is an I

Red/Green/Blue/Amber (RGBA) color mixing applications. Each LED output has its own

8-bit resolution (256 steps) ﬁxed frequency individual PWM controller that operates at

97 kHz with a duty cycle that is adjustable from 0 % to 99.6 % to allow the LED to be set

to a speciﬁc brightness value. An additional 8-bit resolution (256 steps) group PWM

controller has both a ﬁxed frequency of 190 Hz and an adjustable frequency between

24 Hz to once every 10.73 seconds with a duty cycle that is adjustable from 0 % to 99.6 %

that is used to either dim or blink all LEDs with the same value.

Each LED output can be off, on (no PWM control), set at its individual PWM controller

value or at both individual and group PWM controller values. The LED output driver is

programmed to be either open-drain with a 25 mA current sink capability at 5 V or

totem-pole with a 25 mA sink, 10 mA source capability at 5 V. The PCA9635 operates with

a supply voltage range of 2.3 V to 5.5 V and the outputs are 5.5 V tolerant. LEDs can be

directly connected to the LED output (up to 25 mA, 5.5 V) or controlled with external

drivers and a minimum amount of discrete components for larger current or higher voltage

LEDs.

The PCA9635 is one of the ﬁrst LED controller devices in a new Fast-mode Plus (Fm+)

family. Fm+ devices offer higher frequency (up to 1 MHz) and more densely populated bus

operation (up to 4000 pF).

The active LOW Output Enable input pin (OE) allows asynchronous control of the LED

outputs and can be used to set all the outputs to a deﬁned I

state. The OE can also be used to externally PWM the outputs, which is useful when

multiple devices need to be dimmed or blinked together using software control.

Software programmable LED Group and three Sub Call I

deﬁned groups of PCA9635 devices to respond to a common I

for example, all red LEDs to be turned on or off at the same time or marquee chasing

effect, thus minimizing I

126 devices on the same bus.

The Software Reset (SWRST) Call allows the master to perform a reset of the PCA9635

through the I

their default state causing the outputs to be set HIGH (LED off). This allows an easy and

quick way to reconﬁgure all device registers to the same condition.

PCA9635

16-bit Fm+ I

Rev. 07 — 16 July 2009

C-bus, identical to the Power-On Reset (POR) that initializes the registers to

C-bus LED driver

C-bus controlled 16-bit LED driver optimized for

C-bus commands. Seven hardware address pins allow up to

C-bus addresses allow all or

C-bus programmable logic

C-bus address, allowing

Product data sheet

Related parts for PCA9635PW/Q900

PCA9635PW/Q900 Summary of contents

Page 1

PCA9635 16-bit Fm+ I Rev. 07 — 16 July 2009 1. General description The PCA9635 Red/Green/Blue/Amber (RGBA) color mixing applications. Each LED output has its own 8-bit resolution (256 steps) ﬁxed frequency individual PWM controller that operates ...

Page 2

NXP Semiconductors 2. Features I 16 LED drivers. Each output programmable at: N Off Programmable LED brightness N Programmable group dimming/blinking mixed with individual LED brightness I 1 MHz Fast-mode Plus compatible I on SDA output for ...

Page 3

... Keypad backlights for cellular phones or handheld devices 4. Ordering information Table 1. Ordering information Type number Topside mark PCA9635PW PCA9635PW TSSOP28 [1] PCA9635PW/Q900 PCA9635PW TSSOP28 [1] PCA9635PW/Q900 is AEC-Q100 compliant. Contact i2c.support@nxp.com for PPAP. 5. Block diagram SCL INPUT FILTER SDA POWER- RESET V SS REGISTER X BRIGHTNESS CONTROL 24 ...

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... V SS LED8 LED9 LED10 LED11 LED12 PCA9635_7 Product data sheet LED0 LED1 7 PCA9635PW PCA9635PW/Q900 LED2 8 LED3 9 10 LED4 LED5 11 LED6 12 13 LED7 Pin conﬁguration for TSSOP28 Pin description Pin Type Description 1 I address input 0 ...

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NXP Semiconductors Table 2. Symbol LED13 LED14 LED15 SCL SDA Functional description Refer to 7.1 Device addresses Following a START condition, the bus master must output the address of the slave it is accessing. ...

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NXP Semiconductors Fig 3. The last bit of the address byte deﬁnes the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation. 7.1.2 LED all call I • ...

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NXP Semiconductors 7.1.4 Software reset I The address shown in performed by the master. The Software Reset address (SWRST Call) must be used with R/W = logic 0. If R/W = logic 1, the PCA9635 does not acknowledge the SWRST. ...

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NXP Semiconductors Table 3. AI2 Remark: Other combinations not shown in reserved and must not be used for proper device operation. AI[2:0] = 000 is used when the same register must be accessed several times ...

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NXP Semiconductors 7.3 Register deﬁnitions [1][2] Table 4. Register summary Register number (hex ...

Page 10

NXP Semiconductors 7.3.1 Mode register 1, MODE1 Table 5. MODE1 - Mode register 1 (address 00h) bit description Legend: * default value. Bit Symbol Access 7 AI2 read only 6 AI1 read only 5 AI0 read only 4 SLEEP R/W ...

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NXP Semiconductors Table 6. MODE2 - Mode register 2 (address 01h) bit description Legend: * default value. Bit Symbol Access [ OUTNE[1:0] R/W [1] See Section 7.7 “Using the PCA9635 with and without external drivers” mode. Some ...

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NXP Semiconductors 7.3.4 GRPPWM, group duty cycle control Table 8. Legend: * default value Address 12h When DMBLNK bit (MODE2 register) is programmed with logic 0, a 190 Hz ﬁxed frequency signal is superimposed with the 97 kHz individual brightness ...

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NXP Semiconductors 7.3.6 LEDOUT0 to LEDOUT3, LED driver output state Table 10. Legend: * default value. Address 14h 15h 16h 17h LDRx = 00 — LED driver x is off (default power-up state). LDRx = 01 — LED driver x ...

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NXP Semiconductors 7.3.7 SUBADR1 to SUBADR3, I Table 11. Legend: * default value. Address 18h 19h 1Ah Subaddresses are programmable through the I E4h, E8h, and the device(s) will not acknowledge these addresses right after power-up (the corresponding SUBx bit ...

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NXP Semiconductors 7.4 Active LOW output enable input The active LOW output enable (OE) pin, allows to enable or disable all the LED outputs at the same time. • When a LOW level is applied to OE pin, all the ...

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NXP Semiconductors 7.6 Software reset The Software Reset Call (SWRST Call) allows all the devices in the I the power-up state value through a speciﬁc formatted I correctly, it implies that the I bus. The SWRST Call function is deﬁned ...

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NXP Semiconductors Table 14. Use of INVRT and OUTDRV based on connection to the LEDn outputs when INVRT OUTDRV Direct connection to LEDn Firmware 0 0 formulas and LED output state values [2] apply 0 1 formulas ...

Page 18

NXP Semiconductors Table 15. Output transistors based on LEDOUT registers, INVRT and OUTDRV bits when LEDOUT INVRT OUTDRV individual + group dimming/blinking [1] When LED ...

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NXP Semiconductors 8. Characteristics of the I 2 The I C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be ...

Page 20

NXP Semiconductors SDA SCL MASTER TRANSMITTER/ RECEIVER Fig 9. System conﬁguration 8.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed ...

Page 21

NXP Semiconductors 9. Bus transactions slave address START condition (1) See Table 4 for register deﬁnition. Fig 11. Write to a speciﬁc register slave address ...

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NXP Semiconductors slave address START condition R/W acknowledge from slave data from MODE2 register (cont.) A acknowledge from master data from last read byte (cont not acknowledge STOP ...

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NXP Semiconductors 10. Application design-in information V = 2 C-BUS/SMBus MASTER SDA SCL OE ( (typical) for SMBus, Standard-mode or Fast-mode I (2) OE requires ...

Page 24

NXP Semiconductors Question 1: What kind of edge rate control is there on the outputs? • The typical edge rates depend on the output conﬁguration, supply voltage, and the applied load. The outputs can be conﬁgured as either open-drain NMOS ...

Page 25

NXP Semiconductors 11. Limiting values Table 16. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol I/O I O(LEDn tot T stg T amb 12. Static characteristics Table 17. Static characteristics V ...

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NXP Semiconductors Table 17. Static characteristics Symbol Parameter LED driver outputs I LOW-level output current OL I total LOW-level output current OL(tot) I HIGH-level output current ...

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NXP Semiconductors 13. Dynamic characteristics Table 18. Dynamic characteristics Symbol Parameter f SCL clock frequency SCL t bus free time between a BUF STOP and START condition t hold time (repeated) START HD;STA condition t set-up time for a repeated ...

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NXP Semiconductors SDA t BUF t LOW SCL t HD;STA P S Fig 17. Deﬁnition of timing START protocol condition (S) t SU;STA SCL t BUF SDA t HD;STA Rise and fall times refer Fig 18. I ...

Page 29

NXP Semiconductors 15. Package outline TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. ...

Page 30

NXP Semiconductors 16. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 17. Soldering of SMD packages ...

Page 31

NXP Semiconductors • Process issues, such as application of adhesive and ﬂux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath speciﬁcations, including temperature and impurities ...

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NXP Semiconductors Fig 21. Temperature proﬁles for large and small components For further information on temperature proﬁles, refer to Application Note AN10365 “Surface mount reﬂow soldering description” . 18. Abbreviations Table 21. Acronym CDM DUT EMI ESD HBM 2 I ...

Page 33

... NXP Semiconductors 19. Revision history Table 22. Revision history Document ID Release date PCA9635_7 20090716 • Modiﬁcations: Added type number PCA9635PW/Q900 (affects “Pin conﬁguration for PCA9635_6 20080911 PCA9635_5 20070322 PCA9635_4 20061220 PCA9635_3 20061116 PCA9635_2 20060807 PCA9635_1 20060419 PCA9635_7 Product data sheet Data sheet status ...

Page 34

NXP Semiconductors 20. Legal information 20.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualiﬁcation Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...

Page 35

NXP Semiconductors 22. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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