PCA9635PW,112 NXP Semiconductors, PCA9635PW,112 Datasheet
PCA9635PW,112
Specifications of PCA9635PW,112
PCA9635PW
PCA9635PW
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PCA9635PW,112 Summary of contents
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PCA9635 16-bit Fm+ I Rev. 07 — 16 July 2009 1. General description The PCA9635 Red/Green/Blue/Amber (RGBA) color mixing applications. Each LED output has its own 8-bit resolution (256 steps) fixed frequency individual PWM controller that operates ...
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... NXP Semiconductors 2. Features I 16 LED drivers. Each output programmable at: N Off Programmable LED brightness N Programmable group dimming/blinking mixed with individual LED brightness I 1 MHz Fast-mode Plus compatible I on SDA output for driving high capacitive buses I 256-step (8-bit) linear programmable brightness per LED output varying from fully off ...
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... NXP Semiconductors 3. Applications I RGB or RGBA LED drivers I LED status information I LED displays I LCD backlights I Keypad backlights for cellular phones or handheld devices 4. Ordering information Table 1. Ordering information Type number Topside mark PCA9635PW PCA9635PW TSSOP28 [1] PCA9635PW/Q900 PCA9635PW TSSOP28 [1] PCA9635PW/Q900 is AEC-Q100 compliant. Contact i2c.support@nxp.com for PPAP. ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. 6.2 Pin description Table 2. Symbol LED0 LED1 LED2 LED3 LED4 LED5 LED6 LED7 V SS LED8 LED9 LED10 LED11 LED12 PCA9635_7 Product data sheet LED0 LED1 7 PCA9635PW PCA9635PW/Q900 LED2 8 LED3 9 10 LED4 LED5 11 LED6 12 13 ...
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... NXP Semiconductors Table 2. Symbol LED13 LED14 LED15 SCL SDA Functional description Refer to 7.1 Device addresses Following a START condition, the bus master must output the address of the slave it is accessing. There are a maximum of 128 possible programmable addresses using the 7 hardware address pins. Two of these addresses, Software Reset and LED All Call, cannot be used because their default power-up state is ON, leaving a maximum of 126 addresses ...
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... NXP Semiconductors Fig 3. The last bit of the address byte defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation. 7.1.2 LED all call I • Default power-up value (ALLCALLADR register): E0h or 1110 000X • Programmable through I • ...
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... NXP Semiconductors 7.1.4 Software reset I The address shown in performed by the master. The Software Reset address (SWRST Call) must be used with R/W = logic 0. If R/W = logic 1, the PCA9635 does not acknowledge the SWRST. See Section 7.6 “Software reset” Fig 4. Remark: The Software Reset regular I 7 ...
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... NXP Semiconductors Table 3. AI2 Remark: Other combinations not shown in reserved and must not be used for proper device operation. AI[2:0] = 000 is used when the same register must be accessed several times during a single I is overwritten each time the register is accessed during a write operation. ...
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... NXP Semiconductors 7.3 Register definitions [1][2] Table 4. Register summary Register number (hex [1] Only D[4: 0000 to 1 1011 are allowed and will be acknowledged. D[4: 1100 to 1 1111 are reserved and will not be acknowledged. [2] When writing to the Control register, bit 4 must be programmed with logic 0 for proper device operation. ...
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... NXP Semiconductors 7.3.1 Mode register 1, MODE1 Table 5. MODE1 - Mode register 1 (address 00h) bit description Legend: * default value. Bit Symbol Access 7 AI2 read only 6 AI1 read only 5 AI0 read only 4 SLEEP R/W 3 SUB1 R/W 2 SUB2 R/W 1 SUB3 R/W 0 ALLCALL R/W [1] It takes 500 s max. for the oscillator and running once SLEEP bit has been set to logic 0. Timings on LEDn outputs are not guaranteed if PWMx, GRPPWM or GRPFREQ registers are accessed within the 500 s window ...
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... NXP Semiconductors Table 6. MODE2 - Mode register 2 (address 01h) bit description Legend: * default value. Bit Symbol Access [ OUTNE[1:0] R/W [1] See Section 7.7 “Using the PCA9635 with and without external drivers” mode. Some newer LEDs include integrated Zener diodes to limit voltage transients, reduce EMI and protect the LEDs, and these must be driven only in the open-drain mode to prevent overheating the IC ...
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... NXP Semiconductors 7.3.4 GRPPWM, group duty cycle control Table 8. Legend: * default value Address 12h When DMBLNK bit (MODE2 register) is programmed with logic 0, a 190 Hz fixed frequency signal is superimposed with the 97 kHz individual brightness control signal. GRPPWM is then used as a global brightness control allowing the LED outputs to be dimmed with the same value. The value in GRPFREQ is then a ‘ ...
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... NXP Semiconductors 7.3.6 LEDOUT0 to LEDOUT3, LED driver output state Table 10. Legend: * default value. Address 14h 15h 16h 17h LDRx = 00 — LED driver x is off (default power-up state). LDRx = 01 — LED driver x is fully on (individual brightness and group dimming/blinking not controlled). LDRx = 10 — LED driver x individual brightness can be controlled through its PWMx register. LDRx = 11 — ...
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... NXP Semiconductors 7.3.7 SUBADR1 to SUBADR3, I Table 11. Legend: * default value. Address 18h 19h 1Ah Subaddresses are programmable through the I E4h, E8h, and the device(s) will not acknowledge these addresses right after power-up (the corresponding SUBx bit in MODE1 register is equal to 0). Once subaddresses have been programmed to their right values, SUBx bits need to be set to logic 1 in order to have the device acknowledging these addresses (MODE1 register) ...
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... NXP Semiconductors 7.4 Active LOW output enable input The active LOW output enable (OE) pin, allows to enable or disable all the LED outputs at the same time. • When a LOW level is applied to OE pin, all the LED outputs are enabled and follow the output state defined in the LEDOUT register with the polarity defined by INVRT bit (MODE2 register). • ...
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... NXP Semiconductors 7.6 Software reset The Software Reset Call (SWRST Call) allows all the devices in the I the power-up state value through a specific formatted I correctly, it implies that the I bus. The SWRST Call function is defined as the following START command is sent by the I 2 ...
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... NXP Semiconductors Table 14. Use of INVRT and OUTDRV based on connection to the LEDn outputs when INVRT OUTDRV Direct connection to LEDn Firmware 0 0 formulas and LED output state values [2] apply 0 1 formulas and LED output state values [2] apply 1 0 formulas and LED output state values ...
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... NXP Semiconductors Table 15. Output transistors based on LEDOUT registers, INVRT and OUTDRV bits when LEDOUT INVRT OUTDRV individual + group dimming/blinking [1] When LED output state is controlled only by OUTNE[1:0] bits (MODE2 register). [2] External pull-up or LED current limiting resistor connects LEDn to V 7.8 Individual brightness control with group dimming/blinking A 97 kHz fi ...
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... NXP Semiconductors 8. Characteristics of the I 2 The I C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device ...
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... NXP Semiconductors SDA SCL MASTER TRANSMITTER/ RECEIVER Fig 9. System configuration 8.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse ...
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... NXP Semiconductors 9. Bus transactions slave address START condition (1) See Table 4 for register definition. Fig 11. Write to a specific register slave address START condition R/W acknowledge from slave SUBADR3 register (cont.) A acknowledge from slave Fig 12. Write to all registers using the Auto-Increment feature ...
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... NXP Semiconductors slave address START condition R/W acknowledge from slave data from MODE2 register (cont.) A acknowledge from master data from last read byte (cont not acknowledge STOP from master condition Fig 14. Read all registers using the Auto-Increment feature slave address sequence (A) ...
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... NXP Semiconductors 10. Application design-in information V = 2 C-BUS/SMBus MASTER SDA SCL OE ( (typical) for SMBus, Standard-mode or Fast-mode I (2) OE requires pull-up resistor if control signal from the master is open-drain C-bus address = 0010 101x. Fig 16. Typical application PCA9635_7 Product data sheet SDA LED0 SCL LED1 ...
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... NXP Semiconductors Question 1: What kind of edge rate control is there on the outputs? • The typical edge rates depend on the output configuration, supply voltage, and the applied load. The outputs can be configured as either open-drain NMOS or totem-pole outputs. If the customer is using the part to directly drive LEDs, they ...
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... NXP Semiconductors 11. Limiting values Table 16. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol I/O I O(LEDn tot T stg T amb 12. Static characteristics Table 17. Static characteristics Symbol Parameter Supply V supply voltage DD I supply current DD I standby current stb V power-on reset voltage POR Input SCL ...
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... NXP Semiconductors Table 17. Static characteristics Symbol Parameter LED driver outputs I LOW-level output current OL I total LOW-level output current OL(tot) I HIGH-level output current OH V HIGH-level output voltage OH C output capacitance o OE input V LOW-level input voltage IL V HIGH-level input voltage IH I input leakage current ...
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... NXP Semiconductors 13. Dynamic characteristics Table 18. Dynamic characteristics Symbol Parameter f SCL clock frequency SCL t bus free time between a BUF STOP and START condition t hold time (repeated) START HD;STA condition t set-up time for a repeated SU;STA START condition t set-up time for STOP SU;STO condition ...
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... NXP Semiconductors SDA t BUF t LOW SCL t HD;STA P S Fig 17. Definition of timing START protocol condition (S) t SU;STA SCL t BUF SDA t HD;STA Rise and fall times refer Fig 18. I C-bus timing diagram 14. Test information Fig 19. Test circuitry for switching times PCA9635_7 Product data sheet ...
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... NXP Semiconductors 15. Package outline TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 16. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 17. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “ ...
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... NXP Semiconductors • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 17.4 Reflow soldering Key characteristics in reflow soldering are: • ...
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... NXP Semiconductors Fig 21. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 18. Abbreviations Table 21. Acronym CDM DUT EMI ESD HBM 2 I C-bus LED LSB MM MSB NMOS ...
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... NXP Semiconductors 19. Revision history Table 22. Revision history Document ID Release date PCA9635_7 20090716 • Modifications: Added type number PCA9635PW/Q900 (affects “Pin configuration for PCA9635_6 20080911 PCA9635_5 20070322 PCA9635_4 20061220 PCA9635_3 20061116 PCA9635_2 20060807 PCA9635_1 20060419 PCA9635_7 Product data sheet Data sheet status ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 22. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 5 7.1 Device addresses . . . . . . . . . . . . . . . . . . . . . . . 5 2 7.1.1 Regular I C-bus slave address . . . . . . . . . . . . . 5 2 7.1.2 LED all call I C-bus address . . . . . . . . . . . . . . . ...