PCA9620H NXP [NXP Semiconductors], PCA9620H Datasheet - Page 39

• Manufacturer Part Number: PCA9620H
• Description: Universal LCD driver for low multiplex rates
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCA9620
Product data sheet
7.5.3 Timing and frame frequency
7.6 Backplane outputs
Remark: In case that a external clock is used then this clock signal must always be
supplied to the device; removing the clock may freeze the LCD in a DC state, which is not
suitable for the liquid crystal. Removal of the clock is possible when following the correct
procedures. See
The timing of the PCA9620 organizes the internal data flow of the device. This includes
the transfer of display data from the display RAM to the display segment outputs. The
timing also generates the LCD frame frequency which it derives as an integer division of
the clock frequency. The frame frequency is a fixed division of the internal clock or of the
frequency applied to pin CLK when an external clock is used:
When the internal clock is used, the clock and frame frequency can be programmed by
software such that the nominal frame frequency can be chosen in steps of 10 Hz in the
range of 60 Hz to 300 Hz (see
frequency is factory-calibrated with an accuracy of ±15 %.
When the internal clock is enabled at pin CLK by using bit COE, the duty ratio of the clock
may change when choosing different values for the frame frequency prescaler.
on page 9
setting.
The LCD drive section includes eight backplane outputs: BP0 to BP7. The backplane
output signals are generated based on the selected LCD multiplex drive mode.
Table 31
what signal is generated.
Table 31.
[1]
f
Multiplex
drive
mode
1:8
1:6
1:4
1:2
static
fr
=
These pins may optionally be connected to the display to improve drive strength. Connect only with the
corresponding output pin carrying the same signal. If not required they can be left open-circuit.
f
-------
48
clk
describes which outputs are active for each of the multiplex drive modes and
shows the different output duty ratios for each frame frequency prescaler
Mapping of output pins and corresponding output signals with respect to the
multiplex driving mode
Output pin
BP0
Signal
BP0
BP0
BP0
BP0
BP0
All information provided in this document is subject to legal disclaimers.
Figure 12 on page 19
BP1
BP1
BP1
BP1
BP1
BP0
Rev. 1 — 9 December 2010
[1]
Table 17 on page
BP2
BP2
BP2
BP2
BP0
BP0
[1]
[1]
and
BP3
BP3
BP3
BP3
BP1
BP0
Universal LCD driver for low multiplex rates
Figure 13 on page
[1]
[1]
9). Furthermore the nominal frame
BP4
BP4
BP4
BP0
BP0
BP0
[1]
[1]
[1]
BP5
BP5
BP5
BP1
BP1
BP0
20.
[1]
[1]
[1]
PCA9620
BP6
BP6
BP0
BP2
BP0
BP0
© NXP B.V. 2010. All rights reserved.
[1]
[1]
[1]
[1]
Table 17
BP7
BP7
BP1
BP3
BP1
BP0
39 of 71
[1]
[1]
[1]
[1]
(13)