AD6655-125EBZ1 AD [Analog Devices], AD6655-125EBZ1 Datasheet - Page 53

• Manufacturer Part Number: AD6655-125EBZ1
• Description: IF Diversity Receiver
• Manufacturer: AD [Analog Devices]

Addr.
(Hex)
0x104
0x105
0x106
0x107
0x108
0x109
0x10A
0x10B
0x10C
0x10D
0x10E
0x10F
0x110
0x111
Register
Name
Fast Detect
Control
(Local)
Coarse Upper
Threshold
(Local)
Fine Upper
Threshold
Register 0
(Local)
Fine Upper
Threshold
Register 1
(Local)
Fine Lower
Threshold
Register 0
(Local)
Fine Lower
Threshold
Register 1
(Local)
Increase Gain
Dwell Time
Register 0
(Local)
Increase Gain
Dwell Time
Register 1
(Local)
Signal
Monitor
DC
Correction
Control
(Global)
Signal
Monitor
DC Value
Channel A
Register 0
(Global)
Signal
Monitor
DC Value
Channel A
Register 1
(Global)
Signal
Monitor
DC Value
Channel B
Register 0
(Global)
Signal
Monitor
DC Value
Channel B
Register 1
(Global)
Signal
Monitor
SPORT
Control
(Global)
Bit 7
(MSB)
Open
Open
Open
Open
Open
Open
Open
Open
Bit 6
Open
Open
Open
Open
DC
correction
freeze
Open
Open
RMS
magnitude
output
enable
Bit 5
Open
Open
Open
Open
Peak
detector
output
enable
DC Correction Bandwidth(k:[3:0])
Increase Gain Dwell Time[15:8]
Increase Gain Dwell Time[7:0]
Fine Upper Threshold[7:0]
Fine Lower Threshold[7:0]
DC Value Channel A[7:0]
DC Value Channel B[7:0]
Bit 4
Open
Open
Threshold
crossing
output
enable
Rev. 0 | Page 53 of 84
DC Value Channel A[13:8]
DC Value Channel B[13:8]
Bit 3
Open
SPORT SMI SCLK
01 = divide by 2
10 = divide by 4
11 = divide by 8
00 = Undefined
Fast Detect Mode Select[2:0]
Fine Upper Threshold[12:8]
Fine Lower Threshold[12:8]
divide
Bit 2
Coarse Upper Threshold[2:0]
Bit 1
DC
correction
for signal
path
enable
SPORT
SMI SCLK
sleep
Bit 0
(LSB)
Fast detect
enable
DC
correction
for signal
monitor
enable
Signal
monitor
SPORT
output
enable
0x00
0x00
0x00
0x00
0x00
Default
Value
(Hex)
0x00
0x00
0x00
0x00
0x04
AD6655
Default
Notes/
Comments
In ADC clock
cycles
In ADC clock
cycles
Read only
Read only
Read only
Read only