MAX6850 MAXIM [Maxim Integrated Products], MAX6850 Datasheet - Page 21

• Manufacturer Part Number: MAX6850
• Description: 4-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
• Manufacturer: MAXIM [Maxim Integrated Products]

4-Wire Interfaced, 7-, 14-, and 16-Segment Alpha-
Figure 10. Transmission of More than 16 Bits to the MAX6850
Figure 11. VFD Interface Timing Diagram
3) Clock 16 bits of data into DIN, D15 first to D0 last,
4) Take CS high. Positions D7 through D0 in the shift
5) Take SCLK low.
6) Issue another read or write command (which can be
The VFD driver interface on the MAX6850 is a serial
interface using three output pins, VFLOAD, VFCLK, and
VFDOUT (Figure 11) to drive industry-standard, shift-
register, high-voltage grid/anode VFD tube drivers
(Figures 4 and 6). The speed of VFCLK is 1MHz when
DOUT
numeric Vacuum-Fluorescent Display Controller
CLK
observing the setup and hold times. Bit D15 is high,
indicating a read command, and bits D14 through
D8 contain the address of the register to read. Bits
D7 to D0 contain dummy data, which is discarded.
register are now loaded with the data in the register
addressed by bits D15 through D8.
no-op), and examine the bit stream at DOUT; the
first 8 bits contain the address of the register that
was read (Note: The MSB, which was transmitted as
a 1 for a read command, may read back either as a
1 or a zero). The second 8 bits are the contents of
the register addressed by bits D14 through D8 in
step 3.
DIN
CS
VFLOAD
VFDOUT
VFCLK
BIT
1
BIT
______________________________________________________________________________________
2
VFD Driver Serial Interface
N-15
= 0
N-31
N-14
N-30
N-13
N-29
t
VDS
N-12
N-28
DD0
N-11
N-27
t
VCL
N-10
N-26
DD1
t
VCH
N-9
N-25
OSC is 4MHz. The maximum speed of VFCLK is 2MHz
when OSC is 8MHz. This interface is used to transfer
display data from the MAX6850 to the VFD tube driver.
The serial interface bit stream output is programmable
up to 84 bits, which are labeled DD0–DD83.
The functions of the three interface pins are as follows:
VFCLK is the serial clock output, which shifts data on
its falling edge from the MAX6850’s 84-bit output shift
register to VFLOAD.
VFDOUT is the serial data output. The data changes on
VFCLK’s falling edge, and is stable when it is sampled
by the display driver on the rising edge of VFCLK.
VFLOAD is the latch-load output. VFLOAD is high to
transfer data from the display tube driver’s shift register to
the display driver’s output latch (transparent mode), and
low to retain that data in the display driver’s output latch.
A fourth output pin, VFBLANK, provides gating control
of the tube driver. VFBLANK can be configured to be
either high or low using the VBLANK polarity register
(Table 28) to enable the VFD tube driver. In the default
condition, VFBLANK is high to disable the VFD tube dri-
ver, which is expected to force its driver outputs low to
blank the display without altering the contents of its out-
N-8
N-24
N-7
N-23
M-1
N-22
N-6
t
VCP
N-21
N-5
M (M IS VALUE IN SHIFT-LIMIT REGISTER)
N-20
N-4
t
VCSH
N-19
N-3
N-18
t
N-2
VCSW
N-17
N-1
N-16
N
N-15 = 0
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