MAX6850 MAXIM [Maxim Integrated Products], MAX6850 Datasheet - Page 20

• Manufacturer Part Number: MAX6850
• Description: 4-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
• Manufacturer: MAXIM [Maxim Integrated Products]

4-Wire Interfaced, 7-, 14-, and 16-Segment Alpha-
numeric Vacuum-Fluorescent Display Controller
Figure 8. 4-Wire Serial Interface Timing Diagram
Figure 9. 16-Bit Write Transmission to the MAX6850
The MAX6850 contains a 16-bit shift register into which
DIN is clocked on the rising edge of SCLK, when CS is
low. When CS is high, transitions on SCLK have no
effect. When CS goes high, the 16 bits in the shift regis-
ter are parallel loaded into a 16-bit latch. The 16 bits in
the latch are then decoded and executed.
The MAX6850 is written to using the following
sequence:
1) Take SCLK low.
2) Take CS low. This enables the internal 16-bit shift
3) Clock 16 bits of data into DIN, D15 first to D0 last,
4) Take CS high (while SCLK is still high after clocking
20
DOUT
CLK
DIN
CS
register.
observing the setup and hold times. Bit D15 is low,
indicating a write command.
in the last data bit).
______________________________________________________________________________________
SCLK
DOUT
DIN
D15
CS
= 0
D14
Writing Device Registers
D13
D12
D11
t
CSS
t
DS
DN
t
DH
D10
t
D9
CL
DN-1
t
CH
D8
5) Take SCLK low.
Figure 9 shows a write operation when 16 bits are
transmitted.
If fewer or greater than 16 bits are clocked into the
MAX6850 between taking CS low and taking CS high
again, the MAX6850 stores the last 16 bits received,
including the previous transmission(s). The general
case is when n bits (where n > 16) are transmitted to
the MAX6850. The last bits comprising bits {n-15} to {n}
are retained and are parallel loaded into the 16-bit latch
as bits D15 to D0, respectively (Figure 10).
Any register data within the MAX6850 may be read by
sending a logic high to bit D15. The sequence is:
1) Take SCLK low.
2) Take CS low. This enables the internal 16-bit shift
D7
register.
D1
D6
t
D5
CP
D0
D4
t
CSH
Reading Device Registers
D3
t
CSW
D15
t
CSU
D2
D1
D0
D15 = 0