AD9775EB AD [Analog Devices], AD9775EB Datasheet - Page 22

• Manufacturer Part Number: AD9775EB
• Description: 14-Bit, 160 MSPS 2X/4X/8X Interpolating Dual TxDAC+ D/A Converter
• Manufacturer: AD [Analog Devices]

AD9775
SLEEP/POWER-DOWN MODES
(Control Register 00h, Bits 3 and 4)
The AD9775 provides two methods for programmable reduction
in power savings. The sleep mode, when activated, turns off the
DAC output currents but the rest of the chip remains functioning.
When coming out of sleep mode, the AD9775 will immediately
return to full operation. Power-down mode, on the other hand,
turns off all analog and digital circuitry in the AD9775 except
for the SPI port. When returning from power-down mode, enough
clock cycles must be allowed to flush the digital filters of random
data acquired during the power-down cycle.
Figure 16. I
PLL Disabled
Figure 17. I
PLL Disabled
76.0
75.5
75.0
74.5
74.0
73.5
73.0
72.5
72.0
35
30
25
20
15
10
5
0
0
0
AVDD
CLKVDD
8
50
8
50
vs. f
8
vs. f
4
,
4
(MOD. ON)
DATA
4
,
f
f
(MOD. ON)
DATA
DATA
DATA
100
100
vs. Interpolation Rate,
– MHz
– MHz
vs. Interpolation Rate,
150
150
2
,
2
(MOD. ON)
1
1
2
200
200
–22–
ONE/TWO PORT INPUT MODES
The digital data input ports can be configured as two independent
ports or as a single (one port mode) port. In two port mode, the
AD9775 can be programmed to generate an externally avail-
able data rate clock (DATACLK) for the purpose of data
synchronization. Data at the two input ports can be latched into
the AD9775 on every rising clock edge of DATACLK. In one
port mode, P2B12 and P2B13 from input data Port 2 are
redefined as IQSEL and ONEPORTCLK, respectively. The
input data in one port mode is steered to one of the two internal
data channels based on the logic level of IQSEL. A clock signal,
ONEPORTCLK, is generated by the AD9775 in this mode for
the purpose of external data synchronization. ONEPORTCLK
runs at the input interleaved data rate which is 2× the data rate
at the internal input to either channel.
Test configurations showing the various clocks that are required and
produced by the AD9775 in the PLL and one/two port modes
are given in Figures 55 through 58. Jumper positions needed to
operate the AD9775 evaluation board in these modes are given
as well.
PLL ENABLED, TWO PORT MODE
(Control Register 02h, Bits 6–0 and 04h, Bits 7–1)
With the phase-locked loop (PLL) enabled and the AD9775 in
two port mode, the speed of CLKIN is inherently that of the input
data rate. In two port mode, Pin 8 (DATACLK/PLL_ LOCK)
can be programmed (Control Register 01h, Bit 0) to function as
either a lock indicator for the internal PLL or as a clock running
at the input data rate. When Pin 8 is used as a clock output
(DATACLK), its frequency is equal to that of CLKIN. Data at
the input ports is latched into the AD9775 on the rising edge of the
CLKIN. Figure 18 shows the delay, t
rising edge of CLKIN and the rising edge of DATACLK, as well
as the setup and hold requirements for the data at Ports 1 and 2.
Note that the setup and hold times given in Figure 18 are the
input data transitions with respect to CLKIN. t
CLKIN speed, PLL divider setting, and interpolation rate. It is
therefore highly recommended that the input data be synchro-
nized to CLKIN rather than DATACLK when the PLL is enabled.
Note that in two port mode (PLL enabled or disabled), the data
rate at the interpolation filter inputs is the same as the input data
rate at Ports 1 and 2.
The DAC output sample rate in two port mode is equal to the
clock input rate multiplied by the interpolation rate. If zero
stuffing is used, another factor of two must be included to calcu-
late the DAC sample rate.
DATACLK Inversion
(Control Register 02h, Bit 4)
By programming this bit, the DATACLK signal shown in
Figure 18 can be inverted. With inversion enabled, t
refer to the time between the rising edge of CLKIN and the
falling edge of DATACLK. No other effect on timing will occur.
OD
, inherent between the
OD
can vary with
OD
REV. 0
will