AD9775EB AD [Analog Devices], AD9775EB Datasheet - Page 13

• Manufacturer Part Number: AD9775EB
• Description: 14-Bit, 160 MSPS 2X/4X/8X Interpolating Dual TxDAC+ D/A Converter
• Manufacturer: AD [Analog Devices]

MODE CONTROL (VIA SPI PORT)
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
REV. 0
Bit 7
SDIO
Bidirectional
0 = Input
1 = I/O
Filter
Interpolation
Rate
(1×, 2×, 4×, 8×)
0 = Signed Input
Data
1 = Unsigned
0 = PLL OFF
1 = PLL ON
IDAC Fine Gain
Adjustment
IDAC Offset
Adjustment Bit 9
IDAC I
Direction
0 = I
on I
1 = I
I
QDAC Fine Gain
Adjustment
QDAC Offset
Adjustment Bit 9
QDAC I
Direction
0 = I
on I
1 = I
on I
OUTB
OUTB
OUTA
OUTA
OFFSET
OFFSET
OFFSET
OFFSET
OFFSET
OFFSET
on
Bit 6
LSB, MSB First
0 = MSB
1 = LSB
Filter
Interpolation
Rate
(1×, 2×, 4×, 8×)
0 = Two Port Mode
1 = One Port Mode
0 = Automatic
Charge Pump Control
1 = Programmable
IDAC Fine Gain
Adjustment
IDAC Offset
Adjustment Bit 8
QDAC Fine Gain
Adjustment
QDAC Offset
Adjustment Bit 8
Bit 5
Software Reset on
Logic “1”
Modulation
Mode
(None, f
f
DATACLK Driver DATACLK Invert
Strength
IDAC Fine Gain
Adjustment
IDAC Offset
Adjustment Bit 7
QDAC Fine Gain
Adjustment
QDAC Offset
Adjustment Bit 7
S
/4, f
S
/8)
S
/2,
Table I. Mode Control via SPI Port
(Default Values Are Highlighted)
Bit 4
Sleep Mode
Logic “1” shuts down
the DAC output
currents.
Modulation Mode
(None, f
0 = No Invert
1 = Invert
IDAC Fine Gain
Adjustment
IDAC Offset
Adjustment Bit 6
QDAC Fine Gain
Adjustment
QDAC Offset
Adjustment Bit 6
S
/2, f
S
/4, f
–13–
S
/8)
Bit 3
Power-Down Mode
Logic “1” shuts down
all digital and analog
functions.
0 = No Zero Stuffing
on Interpolation
Filters, Logic “1”
enables zero stuffing.
IDAC Fine Gain
Adjustment
IDAC Coarse Gain
Adjustment
IDAC Offset
Adjustment Bit 5
QDAC Fine Gain
Adjustment
QDAC Coarse
Gain Adjustment
QDAC Offset
Adjustment Bit 5
Version Register
Bit 2
1R/2R Mode
DAC output current set
by one or two external
resistors.
0 = 2R, 1 = 1R
1 = Real Mix Mode
0 = Complex
Mix Mode
ONEPORTCLK Invert
0 = No Invert
1 = Invert
PLL Charge Pump
Control
IDAC Fine Gain
Adjustment
IDAC Coarse Gain
Adjustment
IDAC Offset
Adjustment Bit 4
QDAC Fine Gain
Adjustment
QDAC Coarse
Gain Adjustment
QDAC Offset
Adjustment Bit 4
Version Register
Bit 1
PLL_LOCK
Indicator
0 = e
1 = e
IQSEL Invert
0 = No Invert
1 = Invert
PLL Divide
(Prescaler) Ratio
PLL Charge Pump
Control
IDAC Fine Gain
Adjustment
IDAC Coarse Gain
Adjustment
IDAC Offset
Adjustment Bit 3
IDAC Offset
Adjustment Bit 1
QDAC Fine Gain
Adjustment
QDAC Coarse
Gain Adjustment
QDAC Offset
Adjustment Bit 3
QDAC Offset
Adjustment Bit 1
Version Register
–j
+j
AD9775
Bit 0
DATACLK/
PLL_LOCK
Select
0 = PLLLOCK
1 = DATACLK
Q First
0 = I First
1 = Q First
PLL Divide
(Prescaler) Ratio
PLL Charge Pump
Control
IDAC Fine Gain
Adjustment
IDAC Coarse Gain
Adjustment
IDAC Offset
Adjustment Bit 2
IDAC Offset
Adjustment Bit 0
QDAC Fine Gain
Adjustment
QDAC Coarse
Gain Adjustment
QDAC Offset
Adjustment Bit 2
QDAC Offset
Adjustment Bit 0
Version Register